Semiconductor memory device having column select line...

Details Semiconductor memory device having column select line... Semiconductor memory device having column select line...

2005-09-13

2005-09-13

Phung, Anh (Department: 2824)

Static information storage and retrieval

Read/write circuit

Signals

C365S194000, C365S230060, C365S230080

Reexamination Certificate

active

06944069

ABSTRACT:
Provided are a semiconductor memory device with a column select line (CSL) driving scheme capable of reducing skew between column select lines, and a CSL driving method. The semiconductor memory device includes a plurality of CSL enable controllers and a plurality of CSL disable controllers that are installed around corresponding CSL drivers, thereby making loads on input terminals of the CSL drivers almost the same and reducing enable and disable skew between the CSLs. The semiconductor memory device includes a plurality of enable master signal delayers that delay a signal output from a CSL enable master signal generator for different times so as to generate different delay signals and transmit the delay signals to the plurality of CSL enable controllers, and a plurality of disable master signal delayers that delay a signal output from a CSL disable master signal generator for different times so as to generate different delay signals and transmit the delay signals to the plurality of CSL disable controllers. It is possible to compensate for signal delay caused by different loads on signal transmission lines and further reduce enable and disable skew between the CSLs.

REFERENCES:
patent: 6163498 (2000-12-01), Moon
patent: 6359828 (2002-03-01), La
patent: 10-0200766 (1999-03-01), None
patent: 10-0311038 (2001-09-01), None

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