Semiconductor memory device having burn-in test mode and...

Details Semiconductor memory device having burn-in test mode and... Semiconductor memory device having burn-in test mode and...

2011-07-26

2011-07-26

Tu, Christine T (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S718000

Reexamination Certificate

active

07987402

ABSTRACT:
A semiconductor memory device includes: a pattern selector configured to receive a first test control signal and a second test control signal to output a plurality of pattern selection signals and a selection end signal in response to an entry signal; a shifting controller configured to receive the first test control signal and the second test control signal to output a shifting control signal in response to the selection end signal; and a pattern test signal generator configured to select a stress pattern corresponding to the pattern selection signals to generate a plurality of test mode signals for controlling a sequential entry into a plurality of test modes for executing the stress pattern in response to the shifting control signal.

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patent: 6842033 (2005-01-01), Kim et al.
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patent: 01-173499 (1989-10-01), None
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patent: 2005-0065689 (2005-06-01), None

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