Semiconductor memory device having bit line precharger

Static information storage and retrieval – Read/write circuit – Precharge

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365204, 36518525, G11C 700

Patent

active

056711867

ABSTRACT:
A semiconductor memory device includes a bit line, a memory cell, and a precharge circuit responsive to a precharge signal for charging the bit line. The precharge circuit is enabled before cell data is read from the memory cell via the precharged bit line. The memory device further includes a potential controller responsive to the precharge signal for regulating the charge applied to the bit line by the precharge circuit. A charge supplying circuit is coupled to the bit line, and maintains the bit line potential at a predetermined voltage level by providing the bit line with charges during a period from when the precharge circuit completes its precharge operation to when the bit line potential changes in response to reading data from the memory cell.

REFERENCES:
patent: 4879682 (1989-11-01), Engles
patent: 4943945 (1990-07-01), Lai
patent: 5175705 (1992-12-01), Iwahashi
patent: 5309401 (1994-05-01), Suzuki et al.
Roubik Gregorian et al., Integrated Circuits For Signal Processing, 3 pages, 1986, John Wiley & Sons, Inc.
John P. Uyemura, Fundamentals of MOS Digital Integrated Circuits, 5 pages, 1988, Addison-Wesley Publishing Company.

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