Semiconductor memory device having bit line equalizing means

Details Semiconductor memory device having bit line equalizing means Semiconductor memory device having bit line equalizing means

1995-01-17

1996-01-23

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Precharge

365190, 36518901, 365 63, G11C 700

Patent

active

054870445

ABSTRACT:
A semiconductor memory device having memory cells arranged in a matrix, each of the memory cells having input/output terminals, word lines for selecting the memory cells, pairs of bit lines connected to the input/output terminals, bit line pulling-up means for pulling up the potential of the bit lines, bit line loading means connected to another pair of bit lines and bit line equalizing means provided for the bit lines for equalizing the potential of the bit lines by allowing conduction between the bit lines before data is read from a selected memory cell.

REFERENCES:
patent: 4815040 (1989-03-01), Matsui et al.
patent: 4985864 (1991-02-01), Price
patent: 5053997 (1991-10-01), Miyamato et al.
patent: 5091889 (1992-02-01), Hamano et al.
patent: 5093808 (1992-03-01), Foss
Ohtani et al, "A 25ns 1Mb CMOS SRAM", IEEE International Solid-State Circuits Conference, (1987).

Affiliated with

Also associated with

Rating

Semiconductor memory device having bit line equalizing means does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor memory device having bit line equalizing means, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory device having bit line equalizing means will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1509818