Semiconductor memory device having auxiliary memory

Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch

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36523003, 36523008, G11C 700, G11C 800

Patent

active

058187650

ABSTRACT:
A semiconductor memory comprising a memory cell array including a plurality of the memory cells arranged in a matrix, the memory cells being able to be written with and read out data; a reading/writing means for reading and writing data with respect to a selected memory cell; a plurality of auxiliary data storing means arranged in series, a first means among them being connected to the memory cell array and each of the auxiliary data storing means storing a part of the data stored in the memory cell array; a plurality of data output means, each of the data output means being connected to one of the auxiliary data storing means; and a plurality of external data buses, each of the external data buses being connected to one of the data output means; each of the data output means being able to independently output the data stored in a corresponding auxiliary data storing means to a corresponding external data bus.

REFERENCES:
patent: 5719890 (1998-02-01), Thomman et al.

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