Semiconductor memory device having active pull-up circuits

Details Semiconductor memory device having active pull-up circuits Semiconductor memory device having active pull-up circuits

1983-12-15

1986-07-15

Moffitt, James W.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

365203, 365205, 365222, G11C 1140, G11C 700

Patent

active

046010173

ABSTRACT:
A semiconductor memory device comprises active pull-up circuits (APU.sub.1, APU.sub.2) each provided for one bit line (BL.sub.1, BL.sub.1). Each active pull-up circuit (APU.sub.1) has connections to two bit lines. That is, an active pull-up circuit (APU.sub.1) for a first bit line (BL.sub.1) comprises a first transistor (Q.sub.1) connected between a power supply terminal (V.sub.CC) and the first bit line, a second transistor (Q.sub.2) connected between the gate of the first transistor and the first bit line, and a capacitor (C.sub.1) connected to the gate of the first transistor. The gate of the second transistor is connected to a second bit line (BL.sub.1) which is paired with the first bit line. The capacitor receives an active pull-up signal (.phi..sub.AP). A circuit (Q.sub.3, Q.sub.4, Q.sub.5) is provided for transmitting a high level potential to the gate (N.sub.1) of the first transistor to precharge the capacitor.

REFERENCES:
patent: 4028557 (1977-06-01), Wilson
patent: 4262342 (1981-04-01), Tuan
patent: 4481610 (1984-11-01), Takemae et al.
patent: 4504929 (1985-03-01), Takemae et al.

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