Semiconductor memory device having access time control circuit

Details Semiconductor memory device having access time control circuit Semiconductor memory device having access time control circuit

2006-01-24

2006-01-24

Dinh, Son T. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Testing

C365S189080, C365S189110, C365S194000

Reexamination Certificate

active

06990027

ABSTRACT:
Provided is directed to a semiconductor memory device including a control path for enabling a sense generator signal for delaying time as long as a bitline sense amplifier operates in response to a row active signal and enabling a precharge signal according to the sense generator signal, wherein the control path includes: a first time control unit for varying an enabling time of the sense generator signal by each time, according to a special test mode signal for testing the semiconductor memory device and a specific column address; and a second time control unit for varying an enabling time of the precharge signal by each step, according to a special test mode signal for testing the semiconductor memory device and a specific column address.

REFERENCES:
patent: 6104653 (2000-08-01), Proebsting
patent: 6212109 (2001-04-01), Proebsting
patent: 6744684 (2004-06-01), Arimoto et al.
patent: 6885606 (2005-04-01), Kumazaki et al.

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