Static information storage and retrieval – Read/write circuit – Testing
Reexamination Certificate
2000-07-12
2001-11-13
Ho, Hoai V. (Department: 2818)
Static information storage and retrieval
Read/write circuit
Testing
C365S191000, C365S230030
Reexamination Certificate
active
06317373
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device and a semiconductor testing method, and more specifically to a semiconductor memory device having a test mode and a semiconductor testing method utilizing the same.
2. Description of the Background Art
FIG. 9
is a circuit block diagram representing the arrangement of a conventional dynamic random access memory (hereinafter referred to as a DRAM)
30
. Such a DRAM
30
is disclosed, for instance, in Japanese Patent Laying-Open No. 6-295599.
In
FIG. 9
, DRAM
30
is provided with an address buffer circuit
31
, a control signal generating circuit
32
, a memory portion
33
, selectors
34
and
40
, a data input buffer
35
, a comparison data register
36
, a determination circuit
37
, a gate circuit
38
, a determination result register
39
, and a data output buffer
41
.
Address buffer circuit
31
generates row address signals RA
0
to RAn, column address signals CA
0
to CAn, and block selecting signals B
0
and B
1
based on external address signals A
0
to An (n is an integer greater than or equal to 0). Address signals RA
0
to RAn and CA
0
to CAn are provided to memory portion
33
, and block selecting signals B
0
and B
1
are provided to selector
34
. Control signal generating circuit
32
operates in synchronism with an external clock signal CLK, generates a variety of internal control signals according to external control signals /RAS, /CAS, /WE, /OE, and /CS, and controls the entire DRAM
30
.
Memory portion
33
includes four memory blocks
33
a
to
33
d
, and stores one bit of data or four bits of data from selector
34
during a write operation, and reads four bits of data and provides the data to selector
34
and determination circuit
37
during a read operation.
Memory block
33
a
includes a memory array
42
, a sense amplifier+input/output control circuit
43
, a row decoder
47
, and a column decoder
48
, as shown in FIG.
10
. Memory array
42
includes a plurality of memory cells MC arranged in a matrix of rows and columns, a word line WL provided corresponding to each row, and a bit line pair BL and /BL provided corresponding to each column. Each memory cell MC is of the well known type which includes an accessing N-channel MOS transistor and a capacitor for storing information.
Sense amplifier+input/output control circuit
43
includes a data input/output line pair IO and /IO, a column select line CSL provided corresponding to each column, a column select gate
44
, a sense amplifier
45
, and an equalizer
46
. Column select gate
44
includes a pair of N-channel MOS transistors connected between bit line pair BL and /BL and data input/output line pair IO and /IO. Each N-channel MOS transistor has a gate connected to column decoder
48
via column select line CSL. When column decoder
48
raises column select line CSL to the logic high or “H” level or the selected level, a pair of N-channel MOS transistors are rendered conductive, coupling bit line pair BL and /BL to data input/output line pair IO and /IO.
Sense amplifier
45
amplifies the small potential difference between bit line pair BL and /BL to a power-supply voltage VCC according to sense amplifier activating signals SON and ZSOP respectively attaining the “H” level and the logic low or the “L” level. Equalizer
46
equalizes the potentials of bit line pair BL and /BL to a bit line potential VBL (=VCC/2) according to a bit line equalizing signal BLEQ attaining the active level or the “H” level.
Now, the operation of memory block
33
a
shown in
FIG. 10
will be described. During a write operation, column decoder
48
raises to the selected level or the “H” level column select line CSL of the column corresponding to column address signals CA
0
to CAn, and column select gate
44
corresponding to this column select line CSL is rendered conductive.
Thus, the write data from selector
34
is provided to bit line pair BL and /BL of the selected column via data input/output line pair IO and /IO. The write data is provided as a potential difference between bit lines BL and /BL. Then, row decoder
47
raises to the selected level or the “H” level word line WL of the row corresponding to row address signals RA
0
to RAn, and an N-channel MOS transistor of a memory cell MC in the row is rendered conductive. The capacitor of a selected memory cell MC stores the charge of an amount corresponding to the potential of bit line BL or /BL.
During the read operation, first, bit line equalizing signal BLEQ falls to the “L” level, and the equalization of bit lines BL and /BL is interrupted. Then, row decoder
47
raises to the selected level or the “H” level word line WL of the row corresponding to row address signals RA
0
to RAn. The potentials of bit lines BL and /BL slightly change according to the amount of charge of the capacitor in the activated memory cell MC.
Then, sense amplifier activating signals SON and ZSOP respectively attain the “H” level and the “L” level, activating sense amplifier
45
. When the potential of bit line BL is slightly higher than the potential of bit line /BL, the potential of bit line BL is pulled up to the “H” level, and the potential of bit line /BL is pulled down to the “L” level. Conversely, when the potential of bit line /BL is slightly higher than the potential of bit line BL, the potential of bit line /BL is pulled up to the “H” level, and the potential of bit line BL is pulled down to the “L” level.
Then, row decoder
48
raises to the selected level or the “H” level column select line CSL of the column corresponding to column address signals CA
0
to CAn, rendering column select gate
44
of the column conductive. Data on bit line pair BL and /BL of the selected column is provided to selector
34
via column select gate
44
and data input/output line pair IO and /IO. The arrangement and the operation of other memory blocks
33
b
to
33
d
are the same as memory blocks
33
a.
Referring back to
FIG. 9
, selector
34
provides write data DI to each of four memory blocks
33
a
to
33
d
when a test signal TE
10
is at the active level or the “H” level. Selector
34
selects one of four memory blocks
33
a
to
33
d
according to block selecting signals B
0
and B
1
when test signal TE
10
is at the inactive level or the “L” level, and provides read data DO from the selected memory block to selector
40
during a read operation, and provides write data DI to the selected memory block during a write operation. Test signal TE
10
attains the active level or the “H” level during a test, and attains the inactive level or the “L” level during a normal operation. Data input buffer
35
transmits to selector
34
write data DI provided via a data input/output terminal T
0
from outside, according to a write enable signal ZWE attaining the active level or the “L” level.
Comparison data register
36
latches comparison data DC provided from outside via data input/output terminal T
0
and provides comparison data DC to determination circuit
37
according to a latch signal LDC attaining the active level or the “H” level. Determination circuit
37
causes a determination signal JD to attain the “H” level when four bits of data read out from memory portion
33
and comparison data DC all match, and causes determination signal JD to attain the “L” level when they do not match.
Gate circuit
38
inverts determination signal JD generated by determination circuit
37
and provides the inverted signal to a set terminal S of determination result register
39
according to a gate signal GT attaining the active level or the “H” level. When gate signal GT is at the active level or the “H” level, determination circuit
37
and gate circuit
38
are represented by one 5-input EX-OR gate
49
, as shown in FIG.
11
.
Determination result register
39
causes a determination signal JDO to attain the “L” level according to a reset signal RST attaining the active level or the “H” level, and causes determination signal JDO to attain the “H” level accordin
Ho Hoai V.
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
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