Semiconductor memory device having a single data bus line corres

Details Semiconductor memory device having a single data bus line corres Semiconductor memory device having a single data bus line corres

1991-05-20

1993-09-14

Grimm, Siegfried H.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

36518909, 36518911, 365203, G11C 700, G11C 1140

Patent

active

052455734

ABSTRACT:
A semiconductor memory device including data bus lines each having one single wire line, and balance circuits each having an inverter for inverting a corresponding level of the data bus line, a capacitor which is connected at one end with the inverter and at the other end with a power source and has a capacitance substantially similar to the parasitic capacitance of the data bus line, and a transfer gate which receives control signals at a control terminal thereof connected between an end of the capacitor and the data bus line. The balance circuits set the potential level of the respective data bus line at an intermediate level between the power source potential and the ground potential. By structuring the device as above, data could be read out or written in by the data bus line provided in a one-to-one relation with one bit of input/output data to thereby reduce the area of the regions where data bus lines should be placed without impairing the operational speed.

REFERENCES:
patent: 4821232 (1989-04-01), Nakano et al.
patent: 4831590 (1989-05-01), Ichinose
patent: 4870617 (1989-09-01), Nakano et al.

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