Static information storage and retrieval – Read/write circuit – Bad bit
Patent
1995-07-26
1997-10-14
Nelms, David C.
Static information storage and retrieval
Read/write circuit
Bad bit
365201, 3652257, 371 103, G11C 700, G11C 800, G11C 2900
Patent
active
056778813
ABSTRACT:
A semiconductor memory device having a shortened test time and a column selection transistor control method therefor. The semiconductor memory device having a plurality of subarray blocks in row and column directions, the subarray blocks storing a plurality of memory cells, including a row decoder for selecting a row of an arbitrary memory cell of the subarray blocks, a column decoder for selecting a column of an arbitrary memory cell of the subarray blocks, a first circuit for inputting/outputting data to/from a specific memory cell selected by the row and column decoders, a second circuit for dividing the inputted/outputted data into a normal mode and a parallel test mode and inputting/outputting the data, and a column redundancy circuit for constituting a decoding of an address in order to replace a column selection line with a spare column selection line by using only an address input used in the parallel test mode and thereby for activating the spare column selection line to test the memory cells in a wafer state.
REFERENCES:
patent: 5299161 (1994-03-01), Choi et al.
patent: 5406520 (1995-04-01), Tay
patent: 5469401 (1995-11-01), Gillingham
patent: 5550394 (1996-08-01), Sukegawa et al.
Jang Tae-seong
Seo Dong-Il
Nelms David C.
Phan Trong Quang
Samsung Electronics Co,. Ltd.
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