Semiconductor memory device having a hierarchical bit line...

Details Semiconductor memory device having a hierarchical bit line... Semiconductor memory device having a hierarchical bit line...

2008-05-27

2008-05-27

Ho, Hoai V (Department: 2827)

Static information storage and retrieval

Read/write circuit

Precharge

C365S189090, C365S230030

Reexamination Certificate

active

11378384

ABSTRACT:
In semiconductor memory devices having hierarchical bit line structures, a transfer transistor provided between a main bit line and a sub-bit line hinders achievement of a high speed and a low voltage. A sub-bit line SBL in a subarray12is connected via a first transistor PC1to a power source voltage, and via a second transistor NC1to a ground voltage. A main bit line MBLj is connected via a third transistor PD1to the power source voltage. The gate electrodes of the first transistor PC1and the second transistor NC1are connected to the main bit line MBLj, the gate electrode of the third transistor PD1is connected to the sub-bit line SBL. In an initial state, a voltage of the main bit line MBLj is controlled to be at an H level, and voltages of word lines WLi1to Wlip are controlled to be at an L level. When a read operation is performed, the voltage of the main bit line MBLj transitions to the L level, and thereafter, the voltage of a selected word line transitions to the H level.

REFERENCES:
patent: 5561626 (1996-10-01), Fujii
patent: 7251184 (2007-07-01), Nakaya et al.
patent: 06-176592 (1994-06-01), None

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