Semiconductor memory device having a circuit for reducing freque

Static information storage and retrieval – Read/write circuit – Data refresh

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36523006, G11C 700

Patent

active

053331281

ABSTRACT:
A semiconductor memory device of the type needing refresh includes a circuit for reducing the frequency of refresh cycles in data retention mode. A circuit is provided for preventing deterioration to sensing margin of bit lines that may be decreased by a reduction of the frequency of refresh cycles. The deterioration is prevented by increasing the boosting level of word lines.

REFERENCES:
patent: 4570242 (1986-02-01), Nagami
patent: 5161120 (1992-11-01), Kajimoto
patent: 5172341 (1992-12-01), Amin

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