Semiconductor memory device having a burn-in control circuit and

Details Semiconductor memory device having a burn-in control circuit and Semiconductor memory device having a burn-in control circuit and

1996-09-19

1998-03-24

Yoo, Do Hyun

Static information storage and retrieval

Read/write circuit

Testing

365194, G11C 2900

Patent

active

057320322

ABSTRACT:
A burn-in test circuit for a semiconductor memory device tests for defective memory cells. The test circuit applies a test signal that turns "off" transistors in a precharge circuit and applies a select signal to memory cells at predetermined intervals. The select signal and test signal are delayed for different time intervals depending on whether the memory device is transitioning from a normal operating mode to a test mode or from the test mode to the normal operating mode. The selective delay prevents overcurrent conditions from occurring during the mode transitions.

REFERENCES:
patent: 5452253 (1995-09-01), Choi
patent: 5471429 (1995-11-01), Lee et al.
patent: 5541883 (1996-07-01), Devanney

Affiliated with

Also associated with

Rating

Semiconductor memory device having a burn-in control circuit and does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor memory device having a burn-in control circuit and, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory device having a burn-in control circuit and will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2294913