Semiconductor memory device having a bit control circuit

Details Semiconductor memory device having a bit control circuit Semiconductor memory device having a bit control circuit

1996-01-27

1996-04-02

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

36523006, 36523008, G11C 700, G11C 800

Patent

active

055047106

ABSTRACT:
A semiconductor memory device includes a memory cell array. The memory cell array is accessed word by word in response to an address signal. A bit control circuit is operative for generating a bit control signal. An I/O buffer is operative for transmitting data between the memory cell array and an external bus when the memory cell array is accessed. The I/O buffer includes a section for controlling an effective bit or effective bits in one word related to the accessing of the memory cell array in response to the bit control signal, and a section for controlling a position of the effective bit or the positions of the effective bits in one word related to the accessing of the memory cell array in response to the bit control signal.

REFERENCES:
patent: 5268873 (1993-12-01), Suzuki
patent: 5276649 (1994-01-01), Hoshita et al.
patent: 5357469 (1994-10-01), Sommer et al.
patent: 5400292 (1994-03-01), Fukiage et al.

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