Static information storage and retrieval – Read/write circuit – Testing
Reexamination Certificate
2008-07-08
2008-07-08
Hoang, Huan (Department: 2827)
Static information storage and retrieval
Read/write circuit
Testing
C365S200000, C365S203000, C365S230060
Reexamination Certificate
active
07397715
ABSTRACT:
Provided is a semiconductor memory device. The semiconductor memory device includes: a memory cell array including regular cells; a redundancy memory cell array including redundancy cells for substituting for defective regular cells; a command decoder for generating an operation mode selection signal in response to command signals; a redundancy cell test controller for generating a test operation control signal and transmitting address signals in response to the operation mode selection signal; and a redundancy decoder for decoding the address signals to select the redundancy cells in response to the test operation control signal. All redundancy cells can be selected and tested based on the external command signal and the address signal, and thus it is possible to check all redundancy cells for defects in advance even after the semiconductor memory device is packaged, and to enable only non-defective redundancy cells to be substituted for defective regular cells. This increases the reliability of a repair operation.
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Byun Sang-man
Lim Jong-hyoung
Hoang Huan
Mills & Onello LLP
Samsung Electronics Co,. Ltd.
Weinberg Michael J
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