Semiconductor memory device for reducing parasitic...

Details Semiconductor memory device for reducing parasitic... Semiconductor memory device for reducing parasitic...

2001-01-05

2001-11-06

Nelms, David (Department: 2818)

Static information storage and retrieval

Read/write circuit

Precharge

C365S207000, C365S189011, C365S189090, C365S230060

Reexamination Certificate

active

06314038

ABSTRACT:

This application claims the benefit of Korean Patent Application No. 2000-24201 filed on May 6, 2000, which is hereby incorporated by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory, particularly, to a data output path of a semiconductor memory. Although the present invention is suitable for a wide scope of applications, it is particularly suitable for a semiconductor memory device for reducing parasitic capacitance or resistance of the I/O line.
2. Discussion of the Related Art
An I/O (input/output) line transferring data signals that is amplified by a bit line sense amplifier located outside of a cell array has to send the data signals to a specific data output pad, thereby resulting in a long path that reduces its operating speed. Thus, a method of arranging an I/O line to reduce parasitic capacitance or resistance of the I/O line is required.
A method of making the I/O line having a hierarchical structure is widely used for the arrangement of the I/O line. In the hierarchical structure of the I/O line, a path from a memory cell to a data output buffer is hierarchic and a data signal is amplified gradually by placing a sense amplifier at each hierarchy.
Namely, the I/O line having the hierarchical structure amplifies the data signal, which has been amplified by the bit line sense amplifier, through the I/O line and an I/O line sense amplifier, and then amplifies an output of the I/O line sense amplifier again through a data bus and a data bus sense amplifier.
FIG. 1
shows a block diagram of a semiconductor memory according to a related art, specifically illustrating the hierarchically structured I/O line, explained in the above description.
The related art shown in
FIG. 1
is disclosed in U.S. Pat. No. 5,657,265 (
FIG. 2
) which is hereby incorporated by reference in its entirety. The construction of
FIG. 1
will be explained in the following description by referring to the contents taught by U.S. Pat. No. 5,657,265.
Referring to
FIG. 1
, a semiconductor memory of the related art includes a plurality of memory cell array blocks
200
. Each row decoder
30
, formed between two memory cell array blocks, controls a word line of a memory cell array block. A column decoder
40
is arranged respectively to the central direction of a memory cell array block chip to limit a maximum length of a data path of an I/O line
7
arranged vertically. A pair of memory cell array blocks
200
adjacent to each other are arranged near about the center of the chip so that they co-own at least a row decoder
30
. Each of the memory cell array blocks
200
confronting each other at the center of the chip has an independent data output pad.
An I/O switch/driver
8
connected to the respective I/O lines comprises a switch device enabled during reading data and an I/O driver enabled during writing data. The I/O switch/drivers
8
formed at corresponding places of the memory cell array blocks confronting each other are connected to a first data line
20
. The first data line
20
is connected to a data sense amplifier
9
, which is connected to a data I/O buffer/output pad
10
. In order to read or write data simultaneously, a semiconductor memory, such as a synchronous DRAM, pursuing high data transmission bandwidth requires a memory cell array with increased number of I/O lines. As a result, the number of I/O control circuits such as I/O sense amplifiers and I/O drivers are increased in accordance with the increase in the number of I/O lines.
In the such a semiconductor memory according to the related art, data signals outputted from at least four memory cell array blocks are transferred to a data sense amplifier through at least four I/O switches and drivers and a data line, which minimizes the data input/output difference between the I/O switch and the I/O driver. However, the load on the data line is too much since the outputs from the at least four I/O switches and I/O drivers are transferred through the one data line to the data sense amplifier.
Further, the long data line connecting the respective I/O drivers to the output buffer/pad results in increased load. As a result, high speed operation of a semiconductor memory may be prevented since excessive amount of data which requires overtime for driving the data line is loaded on the data line.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to a semiconductor memory that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
The object of the present invention is to provide a semiconductor memory which promptly transfers a data bus signal to high or low level as soon as output of a data signal occurs.
Another object is to provide a semiconductor memory capable of high speed operation.
Additional features and advantages of the invention will be set forth in the description which follows and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, the present invention includes a memory cell array, an I/O line driving circuit, a data bus driving circuit, and a data bus precharge circuit. The memory cell array includes a plurality of memory cells, and outputs a first data signal of the respective memory cells through an I/O line. The I/O line driving circuit generates a second data signal by amplifying the first data signal and is installed in the I/O line. The data bus driving circuit is connected to the I/O line driving circuit to generate a third data signal by amplifying the second data signal. The data bus connects the data bus driving circuit to a data output buffer electrically. The data bus recharge circuit precharges the data bus at a predetermined voltage level before the generation of the third data signal, and transfers the voltage of the data bus to high or low level in accordance with a logic value of the third data signal once the third data signal is generated.
In another aspect, the present invention includes a memory cell array, an I/O line driving circuit, a data bus precharge circuit, a data bus, and a data bus driving circuit. The memory cell array includes a plurality of memory cells and outputs a first data signals of the respective memory cells through an I/O line. The I/O line driving circuit generates a second data signal by amplifying the first data signal. The data bus precharge circuit precharges the data bus to a predetermined voltage level before the generation of the second data signal and transfers the voltage of the data bus to high or low level in accordance with a logic value of the second data signal once the second data signal is generated. The data bus connects the data bus precharge circuit to a data output buffer electrically. The data bus driving circuit generates a third data signal by amplifying a data signal outputted from the data bus precharge circuit.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.


REFERENCES:
patent: 5995431 (1999-11-01), Inui et al.

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