Semiconductor memory device for reducing chip area

Details Semiconductor memory device for reducing chip area Semiconductor memory device for reducing chip area

2006-12-05

2006-12-05

Le, Vu A. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Precharge

C365S222000

Reexamination Certificate

active

07145820

ABSTRACT:
Disclosed is a semiconductor memory device capable of reducing chip area by precharging all banks simultaneously. The semiconductor memory device includes: a command decoder for generating an auto refresh signal in response to an external command; an active information signal generator for generating an active information signal in response to a bank grouping signal when the auto refresh signal is activated; a tRAS controller for generating a tRAS control signal for each bank in response to an activated bank active detection signal, wherein the tRAS control signal maintains an active state during a row active time; a precharge information signal generator for generating a precharge information signal in response to the tRAS control signal of a last activated bank; and a bank control signal generator for generating a bank active signal in response to the active information signal and generates a bank precharge signal in response to the precharge information signal, respectively.

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