Semiconductor memory device for reducing address access time

Details Semiconductor memory device for reducing address access time Semiconductor memory device for reducing address access time

2007-10-02

2007-10-02

Perveen, Rehana (Department: 2116)

Electrical computers and digital processing systems: support

Synchronization of clock or timing signals, data, or pulses

C711S167000

Reexamination Certificate

active

10788550

ABSTRACT:
An apparatus for controlling operations of a synchronous semiconductor memory device, wherein each operation is achieved by a plurality of internal instructions includes a reference clock block for receiving an external clock and outputting a plurality of delayed clock signals; a control block, in response to the plurality of delayed clock signal, for outputting one of the plurality of internal instructions at a first predetermined timing which is earlier than the timing of starting the operation.

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