Semiconductor memory device for preventing skew and timing...

Details Semiconductor memory device for preventing skew and timing... Semiconductor memory device for preventing skew and timing...

2006-03-28

2006-03-28

Le, Thong Q. (Department: 2827)

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

C365S230080

Reexamination Certificate

active

07020029

ABSTRACT:
A semiconductor memory device includes at least memory cell block which has a plurality of memory cells and outputs a plurality of data signals in response to a read command signal; a data latching unit for latching and outputting the plurality of data signals in response to a data output control signal generated in response to the read command signal; a data selection unit for selecting a data output mode from the plurality of data output modes in response to a data selection signal and for outputting data corresponding to the selected data output mode; and a data output control unit for outputting a data selection signal to the data selection unit in response to the data output control signal.

REFERENCES:
patent: 5805504 (1998-09-01), Fujita
patent: 6101136 (2000-08-01), Mochida
patent: 6757212 (2004-06-01), Hamamoto et al.

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