Semiconductor memory device for performing refresh operation

Static information storage and retrieval – Read/write circuit – Data refresh

Reexamination Certificate

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Details

C365S233100

Reexamination Certificate

active

10954530

ABSTRACT:
A memory device according to the present invention includes multiple refresh modes and a refresh controller. A first refresh mode can respectively select one more memory block among a plurality of banks comprising a plurality of blocks and each of all banks. In addition, the first refresh mode may perform a refresh operation with respect to selected memory blocks. The second refresh mode can select a part of the banks and perform a refresh operation of data with a selected bank. The controller may select one of the first and second refresh modes in a refresh operation.

REFERENCES:
patent: 5742554 (1998-04-01), Fujioka
patent: 6154417 (2000-11-01), Kim
patent: 6275895 (2001-08-01), Tabo
patent: 6859407 (2005-02-01), Suh
patent: 6992943 (2006-01-01), Hwang et al.
patent: 2002/0191466 (2002-12-01), Hwang et al.
patent: 2000-52491 (2000-08-01), None
patent: 1020020074723 (2002-04-01), None
patent: 2002-72020 (2002-09-01), None
patent: 1020030025322 (2003-03-01), None
English language abstract of Korean Publication No. 1020030025322.
English language abstract of Korean Publication No. 1020020074723.
English language abstract of Korean Publication No. 2000-52491.
English language abstract of Korean Publication No. 2002-72020.

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