Semiconductor memory device for adjusting impedance of data...

Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch

Reexamination Certificate

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C365S201000

Reexamination Certificate

active

11319615

ABSTRACT:
An apparatus for comparing inputted signals by removing an offset voltage during adjusting an output impedance of a semiconductor memory device, includes a voltage comparator for comparing a first input signal applied to its positive input node with a second input signal applied to its negative input node to output a first output signal to its positive output node and its second output signal to a negative output node; a switched capacitive unit for removing an offset voltage occurred in the positive input node, the negative input node, the positive output node and the negative output node of the voltage comparator; and a latch unit for latching the first output signal and the second output signal.

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