Semiconductor memory device for a low voltage operation

Static information storage and retrieval – Read/write circuit – Precharge

Reexamination Certificate

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C365S230030, C365S210130

Reexamination Certificate

active

11185738

ABSTRACT:
A semiconductor memory includes first and second cell arrays for applying a data signal onto pairs of first bit lines and second bit lines, respectively, first and second reference cell blocks each of which applies a reference signal onto a corresponding bit line bar or a corresponding bit line when the data signal is inputted to the corresponding bit line or the corresponding bit line bar, and a sense amp for sensing and amplifying a difference of data signals applied onto one pair of bit lines connected thereto of the pairs of first and second bit lines, wherein each bit line maintains a floating state without an input of an extra pre-charge voltage upon a pre-charge operation, and the other pair of bit lines disconnected to the sense amp are pre-charged with the reference signal by the corresponding reference cell block.

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patent: 6370072 (2002-04-01), Dennard et al.
patent: 6538942 (2003-03-01), Ferrant
patent: 6678199 (2004-01-01), Joo
patent: 10-340581 (1998-12-01), None
patent: 2005-051044 (2005-02-01), None
patent: 1998-067036 (1998-10-01), None
patent: 10-2004-0065322 (2004-07-01), None
patent: 2004 65322 (2004-07-01), None

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