Semiconductor memory device controlled in synchronous with exter

Details Semiconductor memory device controlled in synchronous with exter Semiconductor memory device controlled in synchronous with exter

1997-07-21

2000-02-01

Dinh, Son T.

Static information storage and retrieval

Read/write circuit

Serial read/write

36518904, 365219, 36523003, 36523005, 365233, G11C 700

Patent

active

06021077&

ABSTRACT:
A semiconductor memory device of the present invention comprises, a first memory cell 110, a first data line DLN connected to the first memory cell, a second data line IOT, a first select signal CSL(E) controlling connection/disconnection between the first data line and the second data line, a second memory cell 112, a third data line DTN connected to the second memory cell, a fourth data line IOT, a second select signal CSL (O) controlling connection/disconnection between the third data line and the fourth data line, wherein a timing selecting the first and second memory cells at the writing operation is the same of a timing selecting the first and second memory cells at the reading operation.

REFERENCES:
patent: 4896294 (1990-01-01), Shimizu et al.
patent: 4945518 (1990-07-01), Muramatsu et al.
patent: 5093805 (1992-03-01), Singh
patent: 5398209 (1995-03-01), Iwakiri et al.
patent: 5524098 (1996-06-01), Holland et al.

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