Semiconductor memory device comprising six-transistor memory cel

Details Semiconductor memory device comprising six-transistor memory cel Semiconductor memory device comprising six-transistor memory cel

1985-04-24

1987-12-01

James, Andrew J.

Static information storage and retrieval

Systems using particular element

Semiconductive

365154, 357 42, 357 59, 357 71, 3072722, H01L 2710, H01L 2904, H01L 2350, G11C 1140

Patent

active

047108975

ABSTRACT:
The gate electrode of a first CMOS inverter is connected to the drains of each transistor of a second CMOS inverter via an interconnection, and the gate electrode of the second CMOS inverter is connected to the drains of the first CMOS inverter via an interconnection, to form a flip-flop circuit. A pair of transfer transistors are connected to the nodes of this flip-flop circuit. A plurality of memory cells each constructed by the flip-flop circuit and the pair of transfer transistors are integrated in a matrix form to form a semiconductor memory device. The pair of gate electrodes are formed of a first polycrystalline silicon layer which includes an impurity of the first conductivity type. The pair of interconnections are formed of an impurity-doped second polycrystalline silicon layer and a high-melting point metal layer, and formed on a first interlayer insulation film. The high-melting point metal layer is provided to prevent an increase in the resistance value due to the formation of a pn junction formed by the interconnections.

REFERENCES:
patent: 4233672 (1980-11-01), Suzuki et al.
patent: 4333099 (1982-06-01), Tanguay et al.
patent: 4481524 (1984-11-01), Tsujide
patent: 4613886 (1986-09-01), Chwang
Dingwall et al., "High-Density, Buried-Contact CMOS/SOS Static RAM's", 1978, IEDM, 193-196.
K. Ochii et al., "An Ultralow Power 8K.times.8-Bit Full CMOS RAM with a Six-Transistor Cell," IEEE Journal of Solid-State Circuits, vol. SC-17, No. 5, Oct. 1982.
C. Anagnostopoulos et al., "Latch-Up and Image Crosstalk Suppression by Internal Gettering," IEEE Journal of Solid-State Circuits, vol. SC-19, No. 1, Feb. 1984.
Patent Abstracts of Japan, vol. 5, No. 125, Aug. 12, 1981, p. (E-69) (797), Referencening JP-A-56-61158, (Suwa Seikosha), May 26, 1981.
PCT Publication WO81/02222 of Aug. 6, 1981.

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