Semiconductor memory device capable of reducing data test...

Details Semiconductor memory device capable of reducing data test... Semiconductor memory device capable of reducing data test...

2001-01-23

2001-10-09

Tran, Andrew Q. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Testing

C365S189070, C365S189020, C365S233100, C365S230030

Reexamination Certificate

active

06301171

ABSTRACT:

TECHNICAL FIELD
The present invention relates generally to semiconductor memory devices and, in particular, to a semiconductor memory device capable of reducing a data test time in a pipeline.
BACKGROUND DESCRIPTION
A semiconductor memory device is composed of a large number of memory cells. When one of these memory cells does not operate normally, the memory device cannot perform its proper function. Moreover, as the integration density of semiconductor memory devices increases, the probability of abnormal operation of memory cells also increases. Accordingly, semiconductor memory devices are tested to sort out defective cells. A bit-by-bit test method and a parallel bit test method have been proposed for testing semiconductor memory devices.
Meanwhile, to improve the performance and increase the speed of semiconductor memory devices, Rambus Dynamic Random Access Memories (DRAMs) have been developed. A Rambus DRAM reads from an entire memory cell array at once, storing a large amount of data and outputting the data at high speed in synchronization with a clock signal. This data transmission is implemented using a pipeline.
FIG. 1
is a diagram illustrating a pipeline in a semiconductor memory, according to the prior art.
In the pipeline of
FIG. 1
, a plurality of unit pipeline cells (UPLs)
110
through
117
(hereinafter collectively referred to as “UPLs
110
-
117
”) are connected in series. Each of the plurality of UPLs
110
-
117
transmits stored data to the succeeding UPL stage and latches data from the preceding UPL stage in response to control signals WRTPIPE, WRTPIPE_B, LOAD and LOAD_B and clock signals TPCLK and TPCLK_B. The signals WRTPIPE_B, LOAD_B and TPCLK_B are the inverted signals of the signals WRTPIPE, LOAD and TPCLK, respectively. In this pipeline, data RD<
0
> through RD<
7
> (hereinafter collectively referred to as “RD<
0
>-RD<
7
>”) of predetermined data bits are sequentially transmitted to a pad DQ
0
via the UPL stages.
FIG. 2
is a timing diagram of some of the signals corresponding the operation of the pipeline of FIG.
1
. Similar to the operation of a typical DRAM, data is read from memory cells corresponding to activated row and column addresses RADR and CADR, respectively, and applied to a data line RD<
7
:
0
>. During a pipeline data read operation in response to a binary logic “low” pipeline write signal WRTPIPE and a preceding stage data latch signal LOAD, read memory cell data RD<
0
>-RD<
7
> are sequentially output in synchronization with the clock signal TPCLK.
However, in the pipeline, output data cannot be tested for defective values until all the data is output in response to the clock signal TPCLK. In other words, the test is performed in bit units. Accordingly, eight edges of the clock signal TPCLK are required for testing the eight data RD<
0
>-RD<
7
>. Rambus DRAMs having a pipeline are composed of a plurality of data lines, so a large number of cycles of the clock signal TPCLK are required for testing one Rambus DRAM. Consequently, the time required to perform a test is undesirably long. Since several million Rambus DRAMs are produced per month, a large amount of time is required to test the same. A long test time increases the cost associated with manufacturing the Rambus DRAMs, as well as decreasing productivity.
Accordingly, it would be desirable and highly advantageous to have a semiconductor memory device capable of reducing the test time of a pipeline therein.
SUMMARY OF THE INVENTION
The problems stated above, as well as other related problems of the prior art, are solved by the present invention, a semiconductor memory device capable of reducing the test time of a pipeline therein.
According to a first aspect of the invention, a semiconductor memory device is provided. The semiconductor to memory device has a pad, data lines, and a data port (DQ) block including a plurality of memory cells. The semiconductor memory device includes a pipeline adapted to output data from selected memory cells of the plurality of memory cells in the DQ block to the pad via the data lines. The pipeline includes a plurality of unit pipeline cells (UPLs) connected in a series. Each of the UPLs is further connected to each of the data lines and is adapted to latch the data, wherein the data is transmitted to a subsequent UPL in the series, if any, so as to sequentially transmit the data to the pad. A comparison controller is connected to a last UPL in the series. The comparison controller is adapted to perform a test for defects in the data and to provide a result of the test to the pad during a test mode, whereby the presence or absence of defects in the DQ block is verified in synchronization with an edge of a clock signal.
According to a second aspect of the invention, a semiconductor memory device is provided. The semiconductor memory device has a pad, a first group of data lines, a second group of data lines, and at least a first and a second data port (DQ) block including a first and a second plurality of memory cells. The semiconductor memory device includes a first pipeline set adapted to output first data from first selected memory cells of the first plurality of memory cells in the first DQ block to the pad via the first group of data lines. The first pipeline set includes a first plurality of unit pipeline cells (UPLs) connected in a first series. Each of the first plurality of UPLs is further connected to each of the first group of data lines and is adapted to latch the first data, wherein the first data is transmitted to a subsequent UPL in the first series, if any, so as to sequentially output the first data to the pad. A second pipeline set is adapted to output second data from second selected memory cells of the second plurality of memory cells in the second DQ block to the pad via the second group of data lines. The second pipeline set includes a second plurality of UPLs connected in a second series. Each of the second plurality of UPLs is further connected to each of the second group of data lines and is adapted to latch the second data, wherein the second data is transmitted to a subsequent UPL in the second series, if any, so as to sequentially output the second data to the pad. A first comparison controller is connected to a last UPL in the first series. The first comparison controller is adapted to test the first data to provided from the first DQ block via the first group of data lines for defects during a test mode. A second comparison controller is connected to a last UPL in the second series. The second comparison controller is adapted to test the second data provided from the second DQ block via the second group of data lines for the defects during the test mode.
When the data on the data lines of a DQ block are tested for defects in the pipeline, the invention requires only one edge of a clock signal due to a structure in which the comparison controller is connected to the last stage of the pipeline, thereby significantly reducing the test time. In addition, the invention can test the data of two DQ blocks using one pad connected to the pipeline of one DQ block, thereby saving the driver of an external tester connected to the pad during the test. In this way, many pads can be saved, so that the drivers of a tester connected to the pads can be used for something else. Therefore, the invention increases the utility of the tester.
These and other aspects, features and advantages of the present invention will become apparent from the following detailed description of preferred embodiments, which is to be read in connection with the accompanying drawings.


REFERENCES:
patent: 5973981 (1999-10-01), Lee
patent: 6144598 (2000-11-01), Cooper et al.

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