Semiconductor memory device capable of realizing a chip with...

Details Semiconductor memory device capable of realizing a chip with... Semiconductor memory device capable of realizing a chip with...

1999-07-01

2001-05-29

Dinh, Son T. (Department: 2824)

Static information storage and retrieval

Floating gate

Particular connection

C365S051000, C365S185110

Reexamination Certificate

active

06240012

ABSTRACT:

BACKGROUND OF THE INVENTION
This invention relates to a semiconductor memory device and more particularly to a nonvolatile semiconductor memory device such as a NAND cell, NOR cell, DINOR cell or AND cell type EEPROM.
As one type of a semiconductor memory device, an EEPROM capable of electrically programming data is known. A NAND cell type EEPROM having NAND cell blocks each constructed by serially connecting a plurality of memory cells has received much attention since it is integrated with high density.
One memory cell in the NAND cell type EEPROM has an FET-MOS structure which has a floating gate (charge storing layer) and control gate stacked on a semiconductor substrate with an insulating film disposed therebetween. A plurality of memory cells are serially connected with the adjacent two of the memory cells commonly using the source/drain to construct a NAND cell and the NAND cell is dealt with as one unit and connected to a bit line. The NAND cells are arranged in a matrix form to construct a memory cell array. Generally, the memory cell array is integrated on a p-type semiconductor substrate or p-type well region.
The drains on one-end sides of the NAND cells arranged in the column direction of the memory cell array are commonly connected to a bit line via selection gate transistors and the sources thereof on the other sides are connected to a common source line via selection gate transistors. The control gates of the memory cells and the gate electrodes of the selection transistors are formed to continuously extend in the row direction of the memory cell array and used as control gate lines (word lines) and selection gate lines.
The operation of the NAND cell type EEPROM with the above construction is as follows. First, the data programming operation is sequentially effected for the memory cells starting from the memory cell which is formed in position farthest away from the bit line contact. A high voltage Vpp (=approx. 20V) is applied to the control gate of the selected memory cell, an intermediate voltage Vmc (=approx. 10V) is applied to the control gates and selection gates of memory cells lying on the bit line contact side with respect to the selected memory cell and a voltage of 0V or intermediate voltage Vmb (=approx. 8V) is applied to the bit line according to data. When 0V is applied to the bit line, the potential is transmitted to the drain of the selected memory cell, thereby causing electrons to be injected from the drain into the floating gate. As a result, the threshold voltage of the selected memory cell is shifted in a positive direction. This state is defined as “1”. On the other hand, if the intermediate voltage Vmb is applied to the bit line, injection of electrons does not occur and the threshold voltage is not changed and is kept negative. This state is defined as “0”.
The data erase operation is effected for all of the memory cells in the selected NAND cell block. That is, all of the control gates in the selected NAND cell block are set to 0V and a high voltage of approx. 20V is applied to the bit line, source line, p-type well region (or p-type semiconductor substrate), and all of the selection gates and control gates in the non-selected NAND cell blocks. As a result, electrons in the floating gates of all of the memory cells in the selected NAND cell block are discharged into the p-type well region (or p-type semiconductor substrate) to shift the threshold voltage in the negative direction.
Further, the data readout operation is effected by setting the control gate of a selected memory cell to 0V, setting the selection gates and control gates of the memory cells other than the selected memory cell to a power supply voltage Vcc and determining whether or not a current flows in the selected memory cell.
Next, the memory cell array, block arrangement and the construction of the NAND cell in the NAND cell type EEPROM are explained in detail.
FIG. 32
shows the block arrangement of the memory cell array in the conventional NAND cell type EEPROM described above. In
FIG. 32
, all of the blocks
1
-
0
to
1
-N in the memory cell array
1
are formed of NAND cells (which are referred to as NAND-A cells) of the same construction. To each of the blocks
1
-
0
to
1
-N, selection gate lines SG
1
, SG
2
and control gate lines CG(
1
) to CG(
8
) are connected. According to a row address, the block and the row of the NAND cell are selected so that a voltage can be supplied to the selection gate lines SG
1
, SG
2
and control gate lines CG(
1
) to CG(
8
) from a row decoder.
FIG. 33
shows an example of the detail construction of part of the memory cell array
1
shown in FIG.
32
and is an equivalent circuit diagram of the memory cell array having the NAND cells arranged in a matrix form. Each of the blocks
1
-
0
to
1
-N in the memory cell array
1
shown in
FIG. 32
corresponds to an area
1
-L (L=0 to N) indicated by broken lines in FIG.
33
. In this example, a NAND cell group commonly having the same word line and selection gate line is called a block and the area
1
-L surrounded by the broken lines in
FIG. 33
is defined as one block. The drain of a selection gate transistor S
1
of each NAND cell is connected to a corresponding one of bit lines BL
1
, BL
2
, . . . , BL
m
and the source of a selection gate transistor S
2
is connected to a common source line CS. Memory cells M
1
, M
2
, . . . , M
8
are serially connected between the source of the selection gate transistor S
1
and the drain of the selection gate transistor S
2
. The operation such as the readout/program operation is generally effected by selecting one block (which is called a selected block) from a plurality of blocks by use of the selection gate transistors S
1
, S
2
.
FIGS. 34A
,
34
B and
FIGS. 35A
,
35
B show in detail one NAND cell extracted from the circuit shown in FIG.
33
.
FIGS. 34A
,
34
B are a pattern plan view and equivalent circuit diagram of a NAND cell portion and
FIGS. 35A
,
35
B are cross sectional views respectively taken along the A-A′ line and B-B′ line of the pattern shown in
FIG. 34A. A
memory cell array formed of a plurality of NAND cells is formed on a p-type silicon substrate (or p-type well region)
11
surrounded by an element isolation oxide film
12
. In this example, eight memory cells M
1
, M
2
, . . . , M
8
are serially connected in each NAND cell.
In each of the memory cells M
1
, M
2
, . . . , M
8
, a floating gate
14
(
14
1
,
14
2
, . . . ,
14
8
) is formed above the substrate
11
with a gate insulating film
13
formed therebetween and a control gate
16
(
16
1
,
16
2
, . . . ,
16
8
) is formed above the corresponding floating gate with a gate insulating film
15
formed therebetween. Further, n-type diffusion layers
19
(
19
1
,
19
2
, . . . ,
19
8
) used as the sources and drains of the memory cells are connected with the sources/drains of the adjacent memory cells commonly used so as to construct the series-connected memory cells M
1
, M
2
, . . . , M
8
.
Selection gates
14
9
,
16
9
and
14
10
,
16
10
which are formed in the same step as the floating gates and control gates of the memory cells are formed on the drain side and source side of the NAND cell. The selection gates
14
9
,
16
9
and
14
10
,
16
10
are electrically connected to each other in an area (not shown) and respectively used as the gate electrodes of the selection gate transistors S
1
, S
2
. The upper surface of the substrate
11
on which the elements are formed is covered with a CVD oxide film (inter-level insulating film)
17
and bit lines are formed on the CVD oxide film
17
. The bit line
18
is formed in contact with a diffusion layer
19
0
on the drain side of one end of the NAND cell. The control gates
14
of the NAND cells arranged in the row direction are respectively commonly arranged as the control gate lines CG(
1
), CG(
2
), . . . , CG(
8
). The control gate lines are used as word lines. The selection gates
14
9
,
16
9
and
14
10
,
16
10
are also arranged continuously in the row

Affiliated with

Also associated with

Rating

Semiconductor memory device capable of realizing a chip with... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor memory device capable of realizing a chip with..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory device capable of realizing a chip with... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2461128