Semiconductor memory device capable of read out mode...

Details Semiconductor memory device capable of read out mode... Semiconductor memory device capable of read out mode...

2008-12-18

2011-10-04

Lappas, Jason (Department: 2827)

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

C365S222000, C365S230080

Reexamination Certificate

active

08031534

ABSTRACT:
A semiconductor memory device is provided that is capable of reading out mode register information stored in a register adapted for LPDDR2 (Low Power DDR2), through DQ pads. The semiconductor memory device includes a mode register control unit configured to receive address signals, a mode register write signal and a mode register read signal and generate a flag signal and at least one output information signal, and a global I/O line latch unit for transferring the output information signal to a global I/O line in response to the flag signal.

REFERENCES:
patent: 7433257 (2008-10-01), Yamagami
patent: 7869297 (2011-01-01), Kim
patent: 2000-030464 (2000-01-01), None
patent: 2004-079841 (2004-03-01), None

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