Semiconductor memory device capable of performing test mode oper

Details Semiconductor memory device capable of performing test mode oper Semiconductor memory device capable of performing test mode oper

1995-12-14

2000-09-19

Dinh, Son T.

Static information storage and retrieval

Read/write circuit

Testing

36518909, 365226, G11C 700, G11C 2900

Patent

active

RE036875&

ABSTRACT:
Disclosed is a DRAM including a test mode operation capable of testing whether a plurality of memory cells are defective or not in a short time. The DRAM includes a power-on detection signal generator, a power-on reset signal generator, and a test mode instruction signal generator. The power-on detection signal generator detects application of a power supply voltage and generates a power-on detection signal. The power-on reset signal generator is reset by a power-on reset signal, counts at least once an external RAS signal applied after reset and generates a power-on reset signal. The test mode instruction signal generator detects logic states of an internal RAS signal, an internal CAS signal and an internal W signal applied after the power-on reset and generates a test mode instructing signal.

REFERENCES:
patent: 4818904 (1989-04-01), Kobauashi
patent: 4905199 (1990-02-01), Miyamoto
patent: 4933902 (1990-06-01), Yamada
patent: 5073874 (1991-12-01), Yamada
patent: 5132937 (1992-07-01), Tuda

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