Semiconductor memory device capable of performing data...

Details Semiconductor memory device capable of performing data... Semiconductor memory device capable of performing data...

2000-08-25

2001-08-07

Dinh, Son T. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Bad bit

C365S049130

Reexamination Certificate

active

06272058

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor memory devices, and more particularly, to a semiconductor memory device that is capable of reading/writing data in units of a plurality of bits.
2. Description of the Background Art
A method for reducing an access time is conventionally known in which a cache memory is placed between a central processing unit (CPU) and a main memory device to copy and store therein a portion of data stored in the main memory device that is frequently accessed.
FIG. 12
is a block diagram showing a configuration of such cache memory. Referring to
FIG. 12
, the cache memory includes a tag memory
71
, a data memory
72
, a logic circuit
73
and a control circuit
74
.
At each address of tag memory
71
, tag data of a plurality of bits (herein, represented by one bit for simplification of the drawing and description) is stored. At each address of data memory
72
, data of a plurality of bits (herein, represented by 2 bits for simplification of the drawing and description) is stored.
Tag memory
71
is provided with an SRAM
71
a
as shown in FIG.
13
. SRAM
71
a
includes a memory array
80
, a redundant memory array
81
, a bit line peripheral circuit
82
, a row decoder
83
, a column decoder
84
, a redundant column decoder
85
and a read/write circuit
86
.
Memory array
80
includes memory cells MC arranged in rows and columns, word lines WL provided corresponding to respective rows, and bit line pairs BLP provided corresponding to respective columns. Redundant memory array
81
has a configuration identical to that of memory array
80
, except that it has fewer columns. Word lines WL are commonly provided for memory array
80
and redundant memory array
81
.
Bit line peripheral circuit
82
performs precharging and equalization of each bit line pair BLP. Row decoder
83
selects one of the plurality of word lines WL according to row address signals RA
0
-RAn (n is an integer at least 0) and drives the word line WL to an H level corresponding to a selected level.
Column decoder
84
is activated when a signal /&phgr;H
1
is at an “H” level, and selects one of the plurality of bit line pairs BLP included in memory array
80
according to column address signals CA
0
-CAn.
Redundant column decoder
85
is activated when a signal &phgr;H
1
is at an “H” level, and selects one of the plurality of bit line pairs BLP included in redundant memory array
81
according to column address signals CA
0
-CAn. Either one of column decoder
84
and redundant column decoder
85
is activated at one time.
Read/write circuit
86
performs reading/writing of data of memory cells MC connected to word line WL selected by row decoder
83
through bit line pair BLP selected by column decoder
84
or redundant column decoder
85
. Read/write circuit
86
is coupled to a logic circuit
73
via a data input/output terminal DQ
1
and a data bus DB
1
.
Data memory
72
includes two SRAMs as shown in FIG.
13
. Column decoders
84
,
84
of these two SRAMs are activated when signals /&phgr;H
2
, /&phgr;H
3
are at an H level, respectively. Redundant column decoders
85
,
85
are activated when signals &phgr;H
2
, &phgr;H
3
are at an H level, respectively. Read/write circuits
86
,
86
of the two SRAMs are coupled to logic circuit
73
through data input/output terminals DQ
2
, DQ
3
and data buses DB
2
, DB
3
, respectively.
Logic circuit
73
receives data DATA from data memory
22
and outputs the data as it is to the outside. It compares tag data received from tag memory
71
with tag data ATD externally supplied, and, when the two tag data match with each other, outputs a signal HIT indicating that the output data DATA is valid, and, when the two tag data mismatch, outputs a signal MISS indicating that the output data is invalid.
Control circuit
74
includes a plurality of program circuits for programming column address signals CA
0
-CAn for designation of defective columns in memories
71
,
72
. Control circuit
74
responds to column address signals CA
0
-CAn and outputs signals &phgr;H
1
, /&phgr;H
1
, &phgr;H
2
, /&phgr;H
2
, &phgr;H
3
and /&phgr;H
3
.
Hereinafter, the operation of the cache memory will be described. When address signals RA
0
-RAn, CA
0
-CAn and tag data ATD are externally supplied, signals &phgr;H
1
and /&phgr;H
1
and signals &phgr;H
2
, /&phgr;H
2
, &phgr;H
3
and /&phgr;H
3
are supplied from control circuit
74
to tag memory
1
and to data memory
72
, respectively. Tag data in tag memory
71
and data in data memory
72
are then read out.
The tag data read out from tag memory
71
is compared with externally supplied tag data ATD at logic circuit
73
. Signal HIT is output when they match, and signal MISS is output when they mismatch. The data DATA read out from data memory
72
is output as it is via logic circuit
73
to the outside.
The conventional cache memory with such configuration as described above is only able to replace the defective column in tag memory
71
with a spare column in tag memory
71
. It is unable to replace the defective column in tag memory
71
with a spare column in data memory
72
. Likewise, the defective column in data memory
72
is only replaceable with a spare column in data memory
72
, not with a spare column in tag memory
71
. Thus, the degree of freedom in redundancy is low, and the yield is poor.
SUMMARY OF THE INVENTION
Therefore, a main object of the present invention is to provide a semiconductor memory device having a high degree of freedom in redundancy.
The semiconductor memory device according to the present invention includes: first to Nth read/write circuits and first to Nth data input/output terminals for performing reading/writing of data of first to Nth memory arrays; an Nth plus one read/write circuit for performing reading/writing of data of a spare memory cell; a control circuit for storing an address signal of a defective memory cell and a number i of a memory array to which the memory cell belongs, and for inactivating the i-th read/write circuit in response to an input of the address signal stored; and a switching circuit for coupling the N plus one read/write circuit with the i-th data input/output terminal in response to the inactivation of the i-th read/write circuit. With such a configuration, it becomes possible to replace a defective memory cell in any of the first to Nth memory arrays with a spare memory cell. Thus, the degree of freedom in redundancy and also the yield increase, compared to the conventional case in which only a defective memory cell in a predetermined memory array was replaceable with a spare memory cell.
Preferably, a plurality of sets of the spare memory cell, the Nth plus one read/write circuit, the control circuit and the switching circuit are provided, and a plurality of sets of the spare memory cell and the Nth plus one read/write circuit are distributed in the vicinity of the first to Nth memory arrays. In this case, flexibility for chip layout increases.
More preferably, a plurality of sets of the spare memory cell, the Nth plus one read/write circuit, the control circuit and the switching circuit are provided, and a plurality of sets of the spare memory cell and the Nth plus one read/write circuit are collectively placed in a predetermined region. In this case, the spare memory cells and the others are placed together in a spare space on the chip, and thus, effective area use is guaranteed.
More preferably, the semiconductor memory device is a cache memory, in which the first to Mth memory arrays constitute a tag memory, and the Mth plus one to the Nth memory arrays constitute a data memory. The cache memory further includes a logic circuit that outputs a signal indicating validity of read data in response to matching between tag data output from the first to Mth data input/output terminals and externally supplied tag data. The present invention is most effective in this case.
The foregoing and other objects, features, aspects and advantages of the present invention will become more a

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