Semiconductor memory device capable of generating internal...

Details Semiconductor memory device capable of generating internal... Semiconductor memory device capable of generating internal...

2003-05-27

2004-07-06

Dinh, Son T. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Differential sensing

C365S196000, C365S206000, C365S207000

Reexamination Certificate

active

06760269

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device and more specifically to a configuration for speeding up a sense amplifier for reading selected memory cell data. More particularly, the present invention relates to a configuration for a high-speed data reading in a static semiconductor memory device.
2. Description of the Background Art
Semiconductor memory devices (simply referred to as a memory hereinafter) include a static memory (SRAM: Static Random Access Memory) having an internal circuit operating statically, a dynamic memory (DRAM: Dynamic Random Access Memory) having an internal circuit operating dynamically and having stored data required to refresh, and a non-volatile memory storing data in a non-volatile manner. These memories are used in various fields depending on their individual characteristics.
FIG. 26
schematically shows a configuration of a main part of a conventional SRAM. In
FIG. 26
, the conventional semiconductor memory includes normal memory cells M arranged in rows and columns.
FIG. 26
representatively shows memory cells M
00
to M
0
n
to Mm
0
to Mmn arranged in a matrix of (m+1) rows and (n+1) columns.
Word lines W
0
to Wm are disposed corresponding to the respective rows of normal memory cells M
00
to Mmn.
FIG. 26
representatively shows a word line W
0
arranged corresponding to normal memory cells Mm
0
to Mmn, a word line Wk arranged corresponding to normal memory cells Mk
0
to Mkn, and a word line Wm arranged corresponding to normal memory cells Mm
0
to Mmn.
A pair of normal bit lines BT and BB are disposed corresponding to each column of normal memory cells M
00
to Mmn.
FIG. 26
representatively shows normal bit lines BT
0
and BB
0
arranged corresponding to normal memory cells M
00
to Mm
0
, and normal bit lines BTn and BBn arranged corresponding to normal memory cells M
0
n
to Mmn. Complementary data are transmitted through paired normal bit line BT (generically representing normal bit lines BT
0
to BTn) and normal bit line BB (generically representing normal bit lines BB
0
to BBn) when a normal memory cell on a corresponding column is selected.
The respective pairs of normal bit lines BT
0
and BB
0
to BTn and BBn are provided with bit line precharge circuits PNC
0
to PNCn each responsive to a precharge signal PRC for precharging normal bit lines BT and BB in a corresponding pair to a prescribed potential (power supply voltage VDD) level. Each of these bit line precharge circuits PNC
0
to PNCn includes a precharge transistor configured of a P channel MOS transistor (an insulated gate type field effect transistor) transmitting power supply voltage VDD to corresponding bit lines BT and BB when conductive, and an equalize transistor configured of a P channel MOS transistor rendered conductive in response to precharge signal PRC and electrically short-circuiting corresponding bit lines BT and BB when made conductive.
Word line drive circuits WD
0
to WDm are provided corresponding to word lines W
0
to Wm, respectively. These word line drive circuits WD
0
to WDm drive corresponding word lines W
0
to Wm to a selected state in accordance with row select signals X
0
to Xm generated by decoding a row address signal (not shown). Each of these word line drive circuits WD
0
to WDm in
FIG. 26
is configured with cascaded inverters of two stages, by way of example.
One of these row select signals X
0
to Xm is driven to H (logic high) level, and a word line corresponding to that row select signal is driven to H level. In other words, a selected word line has a voltage level at H level, and a non-selected word line has a voltage level at L (logic low) level. Therefore, in the state in which a word line is selected, the voltage level of the word line corresponding to the row that is addressed in accordance with a row address signal (not shown) is driven and held at H level, and the voltage level of the remaining word lines (non-selected word lines) is held at L level.
Column select gates PCS
0
to PCSn selectively rendered conductive in response to column select signals Y
0
to Yn are provided corresponding to the respective pairs of normal bit lines BT
0
, BB
0
to BTn, BBn. Each of these column select gates PCS
0
to PCSn includes P channel MOS transistors provided for the respective bit lines BT and BB. By rendering column select gates PCS
0
to PCSn conductive in accordance with column select signals Y
0
to Yn, a normal bit line pair arranged corresponding to a column designated by the column select signals is coupled to a sense amplifier SA.
H level data can be transmitted to the sense amplifier without a threshold voltage loss in the MOS transistor by configuring a column select gate PCS (generically representing column select gates PCS
0
to PCSn) with P channel MOS transistors.
This sense amplifier SA is activated in response to activation of a sense enable signal SE and differentially amplifies the bit line potential transmitted through the selected column select gate to generate internal read data Dout.
A dummy column DSET is provided in order to generate sense enable signal SE to the sense amplifier SA. In dummy column DSET, dummy memory cells D
0
to Dm are disposed sharing the rows with normal memory cells M
00
to Mmn, respectively. These dummy cells D
0
to Dm are respectively connected to word lines W
0
to Wm arranged in corresponding rows.
Dummy bit lines DT and DB are disposed corresponding to dummy memory cells D
0
to Dm. These dummy bit lines DT and DB are provided with a dummy bit line precharge circuit PDC responsive to precharge signal PRC for precharging and equalizing dummy bit lines DT and DB to a prescribed voltage (power supply voltage VDD) level. Similarly to precharge circuits PNC
0
to PNCn, this dummy bit line precharge circuit PDC includes a P channel MOS transistor for equalization and P channel MOS transistors for precharging.
In dummy column DSET, an inverter buffer G
190
for generating sense enable signal SE is provided for dummy bit line DT. More specifically, the internal connection of dummy memory cells D
0
to Dm is set such that L level data is read onto dummy bit line DT.
The memory cells as many as those for each pair of normal bit lines BT
0
, BB
0
to BTn, BBn are connected to dummy bit lines DT and DB. Dummy cells D
0
to Dm and normal memory cells M
00
to Mmn have component transistors of the same size, and the same loads are connected to dummy bit line DT and normal bit lines BB and BT. Therefore a timing at which memory cell data is read on normal bit lines BT
0
, BB
0
to BTn, BBn can be detected by detecting the potential decrease in this dummy bit line DT. Responsively, when memory cell data is read and the potential difference between a pair of normal bit lines exceeds a prescribed value, sense enable signal SE is activated to cause sense amplifier SA to carry out a sensing operation.
FIG. 27
shows the circuit configuration of normal memory cells M
00
to Mmn shown in FIG.
26
. These normal memory cells M
00
to Mmn have the same configuration, and therefore,
FIG. 27
representatively shows a normal memory cell M.
In
FIG. 27
, normal memory cell M includes a P channel MOS transistor PQ
1
connected between a power supply node and a storage node ML and having its gate connected to a storage node MR, a P channel MOS transistor PQ
2
connected between the power supply node and storage node MR and having its gate connected to storage node ML, an N channel MOS transistor NQ
1
connected between storage node ML and a ground node and having its gate connected to storage node MR, an N channel MOS transistor NQ
2
connected between storage node MR and the ground node and having its gate connected to storage node ML, an N channel MOS transistor NQ
3
responsive to a signal on word line W for electrically coupling storage node ML to normal bit line BT selectively, and an N channel MOS transistor NQ
4
selectively rendered conductive in response to a signal on word line W and electrically coupling storag

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