Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate
2000-06-29
2001-06-26
Nelms, David (Department: 2818)
Static information storage and retrieval
Read/write circuit
Bad bit
C365S201000
Reexamination Certificate
active
06252809
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device capable of easily determining the locations of defective memory cells by selectively isolating and testing a redundancy block.
2. Description of the Related Art
The speed and the degree of integration of semiconductor devices have recently increased as a technology of forming fine patterns has developed. In particular, high yield as well as high integration is required for semiconductor memory devices.
Semiconductor memory devices consist of a plurality of memory cells. However, if even one memory cell among the memory cells is defective, the semiconductor memory device cannot operate correctly.
As the degree of integration of semiconductor memory devices increases, the probability that defective memory cells exist becomes higher. Defective memory cells are one of the main causes of reducing the performance of semiconductor memory devices and deteriorating the yield of semiconductor memory devices. Therefore, redundancy circuit technology, which improves yield by replacing defective cells with redundant cells in a semiconductor memory device, is widely used.
In general, redundancy circuits drive redundancy memory cell blocks arranged in redundant rows and columns and select redundant cells in the redundancy memory cell blocks to replace the defective cells. Therefore, when an address signal for designating the defective cells is input, redundant memory cells are selected instead of the defective cells.
A method of replacing defective cells with redundant cells has been disclosed in U.S Pat. No. 5,325,334.
According to this Patent, a plurality of fuses within a fuse box array are programmed so as to be selectively cut or burnt in response to a defective column address signal. A plurality of fuse boxes are arranged in the fuse box array to repair a plurality of defective columns. Each of the fuse boxes shares column address signals corresponding to a defective column, and includes a plurality of fuses which are selectively programmed in response to a corresponding defective column address signal. Thus, if column address signals corresponding to a defective column are input to a fuse box, a redundancy column driver gate is driven in response to a first output signal provided by a block selection control circuit to select a predetermined redundancy column. The selected redundancy column replaces the defective column. In this way, defective cells are replaced by redundancy cells.
The semiconductor memory device is packaged after repairing the defective cells by the method provided in the U.S. Pat. No. 5,325,334, then tested. Since defective cells are replaced by redundant cells, normally, defective cells are not found during testing. However, defective memory cells known as progressive defect cells may be found during testing. Progressive defect occurs in a main memory cell block and a redundancy memory block. It is possible to enhance testing using various test patterns in order to stop the progressive defect at an early stage. By doing so, it is possible to make the test results correct. However, costs are increased since it takes longer to perform the test. Therefore, the number of test patterns is restricted to an appropriate level. It is necessary to determine whether the progressive defect, which occurs after the test, exists in the main memory cell block or the redundancy memory cell block and to feed back the determination result to a process engineer. Then, the process engineer takes a series of measures such as controlling process defects. However, it is difficult to determine the locations of the progressive defective cells by the conventional redundancy method including the method provided in U.S. Pat. No. 5,325,334.
Therefore, a semiconductor memory device capable of easily determining the locations of the progressive defective cells generated after the test of the semiconductor memory device where the defective cells are replaced by the redundant cells, is required.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a semiconductor memory device capable of easily determining whether defective memory cells are located in a main memory block or in a redundancy block by selectively isolating and testing a redundancy block even after packaging the semiconductor memory device.
Accordingly, to achieve the above object, there is provided a semiconductor memory device having a redundancy memory cell block for replacing defective cells by redundant memory cells in order to repair the defective cells in a main memory cell block, wherein a normal mode test for testing the main memory cell block and the redundancy memory cell block and a redundancy isolation mode test for selectively isolating and testing the redundancy memory cell block are adopted, and it is determined whether the defective memory cells found by the normal mode test are located in the main memory block or in the redundancy memory cell block by the redundancy isolation mode test.
According to an embodiment of the present invention, there is provided a semiconductor memory device having a redundancy memory cell block for replacing defective cells by redundant memory cells in order to repair the defective cells in a main memory cell block, comprising a row redundancy selection signal generating circuit for generating a row redundancy selection signal for replacing defective rows including the defective cells by redundancy rows in the redundancy memory cell block, a column redundancy selection signal generating circuit for generating a column redundancy selection signal for replacing defective columns including the defective cells by redundant columns in the redundancy memory cell block, and a redundancy block isolation signal generating circuit for generating a redundancy block isolation signal for isolating the redundancy memory cell block by disabling the row redundancy selection signal and the column redundancy selection signal. In the semiconductor memory device, it is determined whether the defective memory cells found by the normal mode test are located in the main memory block or in the redundancy memory cell block by the redundancy isolation mode test since the redundancy memory cell block is isolated during the test of the semiconductor memory device.
According to the present invention, it is possible to easily determine where defective memory cells are located by generating a redundancy block isolation signal according to a predetermined address and command provided from the outside after packaging chips and selectively isolating and testing the redundancy memory cell array block using the redundancy block isolation signal.
REFERENCES:
patent: 5999480 (1999-12-01), Ong e tal.
Myers Bigel & Sibley & Sajovec
Nelms David
Samsung Electronics Co,. Ltd.
Tran M.
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