Semiconductor memory device capable of correctly and serially re

Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch

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365205, 365221, G11C 1300

Patent

active

053674863

ABSTRACT:
In a serial memory, data signal holding circuits for temporarily holding data read from memory cells are provided as a data register. One holding circuit includes a latch circuit and capacitors connected to input/output nodes of the latch circuit, respectively. The capacitors contribute to stabilizing the latch function by the latch circuit. Therefore, when transistors turn on in response to a serial selection signal at a high level, the latch circuit is prevented from being inverted by the potentials of a serial bus line pair. Accordingly, generation of reading errors is prevented.

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patent: 5058072 (1991-10-01), Kashimura
patent: 5138578 (1992-08-01), Fujii
patent: 5172340 (1992-12-01), Leforestier

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