Semiconductor memory device capable of arbitrarily setting...

Details Semiconductor memory device capable of arbitrarily setting... Semiconductor memory device capable of arbitrarily setting...

2007-07-06

2010-06-29

Kerveros, James C (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

Reexamination Certificate

active

07747912

ABSTRACT:
A semiconductor memory device and related test method are disclosed. Test data is defined from a group of M test bits selected from either input data or corresponding output data. A parallel bit test is then conducted on the test data. The M test bits include N test bits, where N is less than M, selected on a bit by bit basis from the output data, and L test bits, where N+L=M, selected from the input data. The selection of input data may be made in accordance with a don't care case for selected test data.

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