Semiconductor memory device and test method of the same

Details Semiconductor memory device and test method of the same Semiconductor memory device and test method of the same

2006-01-24

2006-01-24

Shin, Christohper (Department: 2182)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

C365S201000, C710S036000

Reexamination Certificate

active

06990617

ABSTRACT:
A semiconductor memory device comprises: a write data controller for receiving predetermined bits of data inputted through data input/output pins to generate plural bits of data, and a read data controller for serially converting the plural bits of data to generate serially converted data through one of the data input/output pins during a test operation; and the write data controller for receiving plural bits of data inputted through the input/output pins to generate the plural bits of data, and the read data controller for receiving the plural bits of data to generate the plural bits of data through the data input/output pins during a regular operation, wherein the number of the plural bits is N times the number of the predetermined bits. N being a natural number.

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