Semiconductor memory device and signal line switching circuit

Details Semiconductor memory device and signal line switching circuit Semiconductor memory device and signal line switching circuit

1999-11-23

2001-06-05

Nguyen, Viet Q. (Department: 2818)

Static information storage and retrieval

Read/write circuit

Multiplexing

C365S189011, C365S230030, C365S230060, C365S230020

Reexamination Certificate

active

06243301

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory device with a so-called “redundancy function”, i.e., preparing a redundant component to repair another equivalent one not functioning correctly due to a defect brought about during the manufacturing process of the device.
FIG. 10
illustrates a configuration of a conventional semiconductor memory device with a redundancy function (see Japanese Laid-Open Publication No. 6-139797). In
FIG. 10
, a memory array
101
includes a plurality of memory cells, each storing data thereon, and a redundant memory array
102
includes a plurality of redundant memory cells to repair defective components possibly included in the memory array
101
.
The semiconductor memory device shown in
FIG. 10
operates in the following manner. When the device is externally accessed, an address input circuit
103
outputs an address signal associated with an address specified. A decoder
104
decodes the address signal and outputs the decoded signal to a data bus switching circuit
109
. At the same time, a redundant driver
105
also generates a signal and provides the signal to the data bus switching circuit
109
. Responsive to the decoded signal, the data bus switching circuit
109
electricaly connects a data line IO to a particular memory cell associated with the specified address in the memory array
101
. Also, responsive to the output signal of the redundant driver
105
, the switching circuit
109
electrically connects a redundant data line RIO to the redundant memory array
102
.
The addresses of defective memory cells are stored in advance in a redundancy decision circuit
106
. Responsive to the address signal, the redundancy decision circuit
106
compares the address specified to those of the defective memory cells. If one of those addresses matches up to the address specified, then the redundancy decision circuit
106
gets the data read out by a data readout amplifier
108
from the redundant memory array
102
and then output by a data output circuit
110
. Alternatively, if none of the addresses match up to the address specified, then the redundancy decision circuit
106
gets the data read out by another data readout amplifier
107
from the memory array
101
and then output by the data output circuit
110
.
In this manner, an externally input address is compared to the pre-stored addresses of defective memory cells, and if the input address matches up to one of those addresses, an equivalent memory cell included in the redundant memory array is accessed to repair the defective memory cell. As a result, the yield of the semiconductor memory device is improved.
In recent years, to improve the data transfer capability of a semiconductor memory device, multi-bit accessing, which makes a multiplicity of memory cells accessible with just one address specified, has been implemented.
If a semiconductor memory device with the conventional redundancy function as shown in
FIG. 10
is accessed by multi-bit accessing, however, the efficiency of repair is poor. For example, suppose just one defective memory cell is included in 128 memory cells corresponding to a single address specified for a 128-bit semiconductor memory device. In such a case, if the address is pre-stored in the redundancy decision circuit to repair the defective memory cell with a redundant one, then not only the single defective memory cell, but also the other normal 127 memory cells are replaced with respective redundant memory cells. In other words, to repair the single defective memory cell, the 127 normal memory cells are all disabled. Thus, such a repair method is far from being efficient.
SUMMARY OF THE INVENTION
An object of the present invention is providing a redundancy function with excellent repair efficiency for a semiconductor memory device of multi-bit accessing type.
Specifically, a semiconductor memory device according to the present invention is adapted to access a multiplicity of bits at a time responsive to a single address specified. The memory device includes: an array of memory cells, which are subdivided into a plurality of memory segments associated with respective addresses; and an internal data bus, which includes the same number of signal lines as the number of bits and transfers data represented by the multiplicity of bits therethrough. Each said memory segment includes: a memory sub-array; and a sub-data bus including a larger number of signal lines than that of the signal lines included in the internal data bus. The signal lines of the sub-data bus are connected to associated bit lines of the memory sub-array for transferring the data in parallel to each other. The array of memory cells includes connection switching means for electrically connecting the signal lines of the internal data bus to associated ones of the signal lines of the sub-data bus to meet a predetermined relationship.
According to the present invention, a plurality of memory segments are provided for respective addresses, and the connection switching means electrically connects the signal lines of the internal data bus to associated signal lines of the sub-data bus, which are connected to respective bit lines in the memory sub-array in each of these memory segments, to meet a predetermined relationship. Thus, data can be transferred through all the signal lines of the sub-data bus but one that is connected to a defective bit line. That is to say, a defective component can be repaired with a redundant component on a bit-by-bit basis, not on an address basis, thus realizing redundancy function with excellent repair efficiency.
In one embodiment of the present invention, the connection switching means preferably disconnects a specific signal line of the sub-data bus from a corresponding signal line of the internal data bus. The specific signal line is associated with a defective bit line or a defective memory cell. The connection switching means shifts connections of signal lines succeeding the specific signal line of the sub-data bus such that the signal line other than the defective signal line of the sub-data bus are connected to the signal lines of the internal data bus.
In this particular embodiment, the connection switching means preferably includes a plurality of first data buses associated with the respective memory segments and a plurality of data bus switching circuits provided for the respective memory segments. Each said data bus switching circuit electrically connects the signal lines of the sub-data bus associated with the memory segment to the signal lines of the first data bus associated with the memory segment to meet the predetermined relationship. The connection switching means further includes a multiplexer for selecting one of the first data buses that is associated with the memory segment specified and connecting the first data bus selected to the internal data bus.
In this particular embodiment, the sub-data buses are preferably placed in parallel to the first data buses. Also, each said memory segment preferably includes a plurality of the memory sub-arrays, and the bit lines of the respective memory sub-arrays in each said memory segment are preferably connected in common to the associated signal lines of the subdata bus in the memory segment.
In an alternate embodiment, each said data bus switching circuit preferably includes: a switch section for electrically connecting each associated pair of signal lines of the first data bus and the sub-data bus to each other; and a switch control section including a plurality of fuses connected in series to each other and controlling the switch section based on terminal potentials of the fuses. In the switch control section, a first-stage one of the fuses is preferably driven by an associated MOS transistor based on a predetermined potential, while each of the other fuses from the second stage on is preferably driven by an associated MOS transistor based on the terminal potential of a previous-stage one of the fuses.
In this particular embodiment, at least one inverter including an MO

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