Semiconductor memory device and semiconductor memory device...

Details Semiconductor memory device and semiconductor memory device... Semiconductor memory device and semiconductor memory device...

2005-11-15

2005-11-15

Nguyen, Tan T. (Department: 2827)

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

C365S195000, C365S233100

Reexamination Certificate

active

06965530

ABSTRACT:
A semiconductor memory device wherein, in continuous data reading, a notification signal to notify whether a suspend mode is entered or not is given synchronously with data output control according to an output control signal with a suspend function, and a method of controlling the device. When an output enable signal is also used as a suspend instruction, a synchronizing circuit synchronizes the output enable signal with a clock signal to output a synchronized output enable signal. This synchronized output enable signal is supplied to a ready control circuit and an output buffer circuit so that the output control of data and ready signal is performed in synchronization with the clock signal. A data terminal goes into a high impedance state in synchronization with the clock signal, which notifies transition to the suspend mode. This quickly notifies that the system bus has become open.

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