Static information storage and retrieval – Read/write circuit – Precharge
Reexamination Certificate
2007-12-18
2007-12-18
Mai, Son L. (Department: 2827)
Static information storage and retrieval
Read/write circuit
Precharge
C365S154000, C365S156000
Reexamination Certificate
active
11522904
ABSTRACT:
In a semiconductor memory device, third and fourth transistors are configured as a vertical structure. The third transistor is laminated over a first transistor, and the fourth transistor is laminated over a second transistor, whereby a reduction in cell area is achieved. A voltage, which is set on the condition that the difference between a source potential applied to each of the first and second transistors and the potential of a select level of a word line becomes greater than or equal to a threshold voltage of each of the third and fourth transistors, is supplied to a source electrode of each of the first and second transistors, to thereby perform “0” write compensation.
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Takahashi Yasuhiko
Tanaka Takayuki
Antonelli, Terry Stout & Kraus, LLP.
Mai Son L.
Renesas Technology Corp.
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