Semiconductor memory device and on-die termination circuit

Details Semiconductor memory device and on-die termination circuit Semiconductor memory device and on-die termination circuit

2009-05-20

2011-10-25

Ismail, Shawki (Department: 2819)

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

Bus or line termination

Reexamination Certificate

active

08044680

ABSTRACT:
An on-die termination (ODT) circuit including drive signal generators, each drive signal generator configured to generate a corresponding plurality of ODT drive signals; and ODT drive units, each ODT drive unit configured to terminate a corresponding terminal with a termination resistance in response to the ODT drive signals of a corresponding drive signal generator. The drive signal generators are configured to supply the ODT drive signals to the ODT drive units to output a plurality of ODT control signals through the terminals in a test mode.

REFERENCES:
patent: 7164611 (2007-01-01), Kinsley
patent: 2006/0255830 (2006-11-01), Kim
patent: 2007/0222476 (2007-09-01), Lee
patent: 2008/0315913 (2008-12-01), Kim
patent: 2007-257822 (2007-10-01), None
patent: 2003-0083237 (2003-10-01), None
patent: 2003-0090955 (2003-12-01), None
patent: 2004-0055879 (2004-06-01), None
patent: 2007-0036552 (2007-04-01), None
patent: 2007-0096214 (2007-10-01), None
patent: 10-0780962 (2007-11-01), None

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