Semiconductor memory device and methods thereof

Details Semiconductor memory device and methods thereof Semiconductor memory device and methods thereof

2007-02-06

2010-12-14

Trimmings, John P (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

C714S724000, C324S765010, C365S201000, C716S030000

Reexamination Certificate

active

07853840

ABSTRACT:
A semiconductor memory device and methods thereof are provided. The example semiconductor memory device may include an internal address generating circuit operating in accordance with a first addressing protocol during normal operation and operating in accordance with a second addressing protocol during a test operation, the first addressing protocol associated with a first number of clock cycles for transferring a memory address and the second addressing protocol associated with a second number of clock cycles for transferring a memory address, the first number of clock cycles being greater than the second number of clock cycles. An example method may for achieving an single pumped address (SPA) mode in a semiconductor memory device configured for a double pumped address (DPA) mode may include receiving a first external address, generating a first internal address corresponding to the received first external address, receiving a second external address, generating a second internal address corresponding to the received second external address and delaying the generation of the first internal address to reduce a clock cycle interval between the generated first and second internal addresses.

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Decision of Grant dated Sep. 14, 2007 issued in corresponding Korean application No. 10-2006-0063779.

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