Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
2006-02-06
2009-10-20
Ellis, Kevin L (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C714S718000, C714S724000, C714S733000, C714S738000, C365S200000, C365S201000
Reexamination Certificate
active
07607055
ABSTRACT:
A semiconductor memory device includes at least one first built in self test (BIST) circuit configured to generate test pattern data, and at least one second BIST circuit configured to receive the test pattern data as received test pattern data and compare the received test pattern data to the test pattern data.
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Jung Dae-Hee
Park Chul-Woo
Seo Seung-Young
Ellis Kevin L
Marger & Johnson & McCollom, P.C.
McMahon Daniel F
Samsung Electronics Co,. Ltd.
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