Semiconductor memory device and method of testing the same

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing

Reexamination Certificate

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Details

C714S718000, C714S724000, C714S733000, C714S738000, C365S200000, C365S201000

Reexamination Certificate

active

07607055

ABSTRACT:
A semiconductor memory device includes at least one first built in self test (BIST) circuit configured to generate test pattern data, and at least one second BIST circuit configured to receive the test pattern data as received test pattern data and compare the received test pattern data to the test pattern data.

REFERENCES:
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patent: 6195771 (2001-02-01), Tanabe et al.
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patent: 7197676 (2007-03-01), Co et al.
patent: 7216278 (2007-05-01), Andreev et al.
patent: 2003/0070126 (2003-04-01), Werner et al.
patent: 2006/0282722 (2006-12-01), Co et al.
patent: 08-329698 (1996-12-01), None
patent: 2004-093421 (2004-03-01), None
patent: 1999-69337 (1999-09-01), None
English language abstract of Korean Publication No. 1999-69337.
English language abstract of Japanese Publication No. 08-329698.
English language abstract of Japanese Publication No. 2004-093421.

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