Semiconductor memory device and method of testing same

Details Semiconductor memory device and method of testing same Semiconductor memory device and method of testing same

2011-03-22

2011-03-22

Ton, David (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Replacement of memory spare location, portion, or segment

C714S718000

Reexamination Certificate

active

07913126

ABSTRACT:
Provided is a semiconductor memory device in which it is possible to conduct a parallel test by comparison with an expected value after replacement with a redundant cell. The memory device includes a logic circuit for outputting an activated redundant hit signal when at least one determination circuit of determination circuits corresponding to respective ones of a plurality of redundant addresses is activated; a logic circuit for outputting an activated signal when all outputs of the circuits are inactive; and a selector for outputting a test-result mask signal when a redundant area is tested, and outputting the output of the logic circuit when a normal area is tested. The test result is forcibly passed when a memory array is tested and when a redundant address is accessed.

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