Semiconductor memory device and method of performing a...

Details Semiconductor memory device and method of performing a... Semiconductor memory device and method of performing a...

2007-03-30

2010-02-02

Kerveros, James C (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

Reexamination Certificate

active

07657800

ABSTRACT:
A semiconductor memory device and method directed to performing a memory operation in a semiconductor memory device, which include receiving data and a data masking signal corresponding to a portion of the received data configured to be written into memory in response to a write command and the data masking signal configured to block the at least a portion of the received data from being written into the memory, and further configuring different timing parameters of the received data and the data masking signal for executing the write command without writing the at least a portion of the received data into the memory.

REFERENCES:
patent: 6188639 (2001-02-01), Sakakibara
patent: 6192429 (2001-02-01), Jeong et al.
patent: 6252804 (2001-06-01), Tomita
patent: 6411564 (2002-06-01), Ikeda

Affiliated with

Also associated with

Rating

Semiconductor memory device and method of performing a... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor memory device and method of performing a..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory device and method of performing a... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4167276