Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2011-04-06
2011-12-13
Chiang, Jack (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S257000, C438S926000, C438S593000, C438S264000, C257SE27103, C257S316000, C257S318000, C257S328000
Reexamination Certificate
active
08076205
ABSTRACT:
A semiconductor memory includes a memory cell array area provided with first and second memory cells and having a first active area and a first element isolation area constituting a line & space structure, and having a floating gate electrode and a control gate electrode in the first active area, a word line contact area adjacent to the memory cell array area and having a second active area, first and second word lines with a metal silicide structure, functioning respectively as the control gate electrodes of the first and second memory cells and arranged to straddle the memory cell array area and the word line contact area. A dummy gate electrode is arranged just below the first and second word lines in the second active area.
REFERENCES:
patent: 7786524 (2010-08-01), Hazama
patent: 7884414 (2011-02-01), Watanabe
patent: 7977190 (2011-07-01), Aritome
patent: 2010/0155814 (2010-06-01), Sato et al.
patent: 2010/0184275 (2010-07-01), Takeuchi et al.
patent: 2007-73887 (2007-03-01), None
Baptiste Wilner Jean
Chiang Jack
Kabushiki Kaisha Toshiba
Oblon, Spivak McClelland, Maier & Neustadt, L.L.P.
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