Semiconductor memory device and method of fabricating the same

Details Semiconductor memory device and method of fabricating the same Semiconductor memory device and method of fabricating the same

2001-03-07

2002-12-03

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C257S306000

Reexamination Certificate

active

06489197

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the technique relating to a semiconductor memory device and more particularly, to a semiconductor memory device (e.g., a Dynamic Random-Access Memory, a DRAM) with the so-called cylindrical capacitor structure, and a method of fabricating the device.
2. Description of the Related Art
Recently, the tendency to decrease the memory cell size or area has been progressing with the increasing storage capacity and the rising integration-scale or density. In particular, with the storage cell of DRAMS, the two-dimensional size of the storage capacitor for storing electric charge needs to be decreased without reducing the essential capacitance value of each storage cell for normal operation. Thus, to meet this need, various three-dimensional capacitor structures (e.g., the cylindrical stacked capacitor, fin-like stacked capacitor, and so forth) have ever been developed and some of them have been actually applied to manufacture. Some examples of them are disclosed in the Japanese Non-Examined Patent Publication Nos. 10-189910 published in July 1988 and 10-22483 published in January 1998.
With the conventional DRAMS of this type, the conductive contact pads in the storage cells are formed to fill the contact holes in an interlayer dielectric layer according to the minimum design rule. Thus, it has become difficult to form stably a patterned photoresist film for the contact pad. Also, due to the reduction of the alignment margin, electrical short-circuit tends to occur between the wiring lines and the storage capacitors.
An example of the conventional methods of fabricating the DRAM with the cylindrical stacked capacitor structure is explained below with reference to FIGS.
1
and
FIGS. 2A
to
2
D.
The conventional DRAM has a typical configuration shown in
FIG. 1
, which includes active areas
116
formed in a semiconductor substrate
101
. The areas
116
are arranged regularly in the substrate
101
. Two Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs, not shown) are formed in each of the areas
116
. Bit lines
107
and gate electrodes
114
of the MOSFETS are arranged in a matrix array over the substrate
101
. The gate electrodes
114
are formed to be consecutive and serve as word lines. The bit lines
107
extend in the X direction while the gate electrodes (i.e., word lines)
114
extend in the Y direction.
Each of the active areas
116
includes two source regions and a common drain region of the two adjoining MOSFETs. The common drain region is electrically connected to the overlying, corresponding bit line
107
by way of a conductive contact pad
106
.
Each of the two source regions is electrically connected to the overlying, lower electrode of the corresponding storage capacitor by way of the corresponding contact pad
106
. The lower electrode has an approximately rectangular pattern (i.e., the plan shape), as shown in FIG.
1
.
The conventional DRAM having the configuration shown in
FIG. 1
is fabricated in the following way.
First, as shown in
FIG. 2A
, an isolation dielectric
102
is selectively formed in the substrate
101
by the known Shallow Trench Isolation (STI) method, forming the active areas
116
. A specific impurity is selectively ion-implanted into the areas
116
, forming the diffusion regions (e.g., source/drain regions)
103
. Thereafter, MOSFETs are formed in the areas
116
using the regions
103
through known processes.
Subsequently, a first interlayer dielectric film
104
, which is made of, for example, a borophosphor silicate glass (RPSG), is deposited over the whole substrate
101
and then, the surface of the film
104
is planarized by the chemical-mechanical polishing (CMP) method. After a patterned photoresist film (not shown) is formed on the film
104
thus planarized, the film
104
is selectively etched using the photoresist film as a mask. Thus, contact holes
105
for the conductive contact pads
106
are formed over the diffusion regions
103
which will be electrically connected to the overlying bit lines
107
and the overlying lower capacitor electrodes.
Following this, a polysilicon film (not shown) is formed on the first interlayer dielectric film
104
and etched back by a dry etching process, thereby forming polysilicon contact pads
106
to fill the respective holes
105
. The state at this stage is shown in FIG.
2
A.
Next, the bit line
107
are formed on the first interlayer dielectric film
104
, as shown in FIG.
2
B. Specifically, a tungsten polycide film and a silicon nitride film (both of which are not shown) are successively deposited on the film
104
and then, they are selectively etched by dry etching processes using the same patterned photoresist film as a mask. Thus, the bit lines
107
are formed on the film
104
by the remaining tungsten polycide film while dielectric caps
108
are formed on the tops of the lines
107
by the remaining silicon nitride film.
The bit line
107
located at approximately the middle in
FIG. 2B
is contacted with the underlying polysilicon contact pad
106
. Unlike this, the bit lines
107
located at the left and right sides in
FIG. 2B
are slightly contacted with the underlying contact pads
106
, respectively. This is undesired contact.
A silicon nitride film (not shown) is deposited on the first interlayer dielectric film
104
to cover the bit lines
107
with the caps
108
. The silicon nitride film is then etched back by a dry etching process, forming sidewalls
109
at each side of each bit line
107
, as shown in FIG.
2
C. Thus, the top and both sides of each line
107
are entirely covered with silicon nitride. The state at this stage is shown in FIG.
2
C.
A second interlayer dielectric film
110
, which is thicker than the first interlayer dielectric film
104
, is deposited on the film
104
over the whole substrate
101
to cover the bit lines
107
with the caps
108
and the sidewalls
109
. The surface of the film
110
is then planarized by a CMP process. A patterned photoresist film (not shown) is formed on the film
110
and then, the film
110
is selectively etched by a dry etching process, thereby forming openings
111
in the film
110
for the lower capacitor electrodes. As shown in
FIG. 1
, the openings
111
are approximately rectangular in plan shape. This dry etching process is performed under the condition that the etch selectivity is sufficiently high between BPSG (i.e., the film
110
) and silicon nitride (i.e., the caps
108
and the sidewalls
109
). For example, a gaseous mixture of CHF
3
and CO is used for this purpose.
Thereafter, a polysilicon film (not shown) is deposited on the interlayer dielectric film
110
to extend along the inner walls of the openings
111
. Using a patterned photoresist film as a mask, the polysilicon film thus deposited is selectively etched by a dry etching process, forming the lower electrodes of the capacitors.
With the above-mentioned method of fabricating the conventional DRAM with reference to
FIGS. 2A
to
2
D, there are the following problems.
The first problem is that electrical short-circuit tends to occur between the contact pad
106
in each opening
111
and the adjoining bit line
107
. This is because the contact holes
105
in the first interlayer dielectric layer
104
are formed according to the minimum design rule and therefore, the alignment margin is extremely small between the opening
111
and the line
107
.
As shown in
FIG. 2D
, the bottoms of the bit lines
107
located at approximately the left and right sides are in undesired contact with the tops of the respective contact pads
106
.
The second problem is that the bit lines
107
tend to be undesirably etched in the dry etching process of forming the openings
111
in the second interlayer dielectric film
110
due to the reason described below.
The width of the bit line
107
may be decreased to avoid the first problem. In this case, however, the surface areas of the caps
108
and the sidewalls
109
(both of which are made of sili

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