Semiconductor memory device and method of controlling the same

Details Semiconductor memory device and method of controlling the same Semiconductor memory device and method of controlling the same

2002-11-18

2004-08-03

Auduong, Gene (Department: 2818)

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

C365S189040, C365S230040, C365S230060

Reexamination Certificate

active

06771546

ABSTRACT:

CROSS REFERENCE TO RELATED APPLICATION
This application claims benefit of priority under 35 U.S.C. §119 to Japanese Patent Application No. 2002-272022, filed on Sep. 18, 2002, the entire contents of which are incorporated by reference herein.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device and a method of controlling the same, and particularly relates to an FBC (Floating Body Cell) structured semiconductor memory device and a method of controlling the same.
2. Related Background Art
An FBC memory is a volatile memory which can be formed on an SOI substrate and expected as a semiconductor memory device which replaces DRAMs. The FBC memory has an advantage of being suitable for high-density integration because of its small cell size. The basic explanation of this FBC memory is disclosed, for example, in document 1 (T. Ohsawa et al., “Memory Design Using One-Transistor Gain Cell on SOI”, ISSCC Digest of Technical Papers, pp152-153, 2002).
FIG. 30
is a plane layout of a memory cell array portion of the FBC memory,
FIG. 31
is a sectional view taken along the line A-A′ of the memory cell array in
FIG. 30
,
FIG. 32
is a sectional view taken along the line B-B′ of the memory cell array in
FIG. 30
, and
FIG. 33
is a sectional view taken along the line C-C′ of the memory cell array in FIG.
30
.
FIG. 34
is a circuit diagram showing an equivalent circuit of this memory cell array.
As can be seen from these drawings, the FBC memory uses MIS transistors (Metal-Insulator-Semiconductor transistors) arranged in a matrix form on the SOI substrate as memory cells MC. In an example shown in these drawings, the SOI substrate includes an N
+
-type diffusion layer
12
formed on a P-type semiconductor substrate
10
and an insulating film (a silicon oxide film, for example)
14
formed on the diffusion layer
12
. Moreover, this memory cell array includes a plurality of word lines WL extending in a first direction, a plurality of source lines SL extending also in the first direction, and a plurality of bit lines BL extending in a second direction which intersects the first direction.
A drain
20
of the memory cell MC is connected to the bit line BL via a bit line contact
21
, a source
22
is connected to the source line SL, and a gate electrode
24
constitutes the word line WL. A portion between the drain
20
and the source
22
is electrically in a floating state and forms a channel body
28
. The aforementioned gate electrode
24
is located above this channel body
28
with a gate insulating film
26
therebetween. The source line SL is always fixed to 0 V.
The drain
20
and the source
22
of the memory cell MC are formed by an N-type semiconductor layer, and the channel body
28
is formed by a P-type semiconductor layer. The memory cell MC stores data depending on whether or not holes which are majority carriers are accumulated. Hereafter, a state in which holes are accumulated in the channel body
28
is defined as “1” and a state in which holes are not accumulated therein is defined as “0”.
N
+
-type polysilicon pillars
30
shown in FIG.
32
and
FIG. 33
are each an electrode formed to maintain the accumulation state of holes. Namely, the polysilicon pillar
30
and the channel body
28
form capacitance, and by applying negative voltage to the polysilicon pillar
30
, the accumulation state of holes can be maintained for a longer time. However, the holes accumulated in the channel body
28
come off the channel body
28
after a lapse of a sufficiently long time because of leakage from a PN junction portion which exists in the drain
20
and the source
22
. Therefore, it is necessary to execute a data refresh in the FBC memory likewise with the DRAM.
Next, the operational principle of the FBC structured memory cell MC will be explained. When data “1” is written into the FBC structured memory cell MC, as shown in
FIG. 35
, for example, 1.5 V is applied to the word line WL and 1.5 V is applied to the bit line BL. Since a transistor composing the memory cell MC operates in a saturation region, holes are generated by impact ionization. The generated holes move to the lower side of the channel body
28
and they are accumulated in the capacitance.
When data “0” is written, as shown in
FIG. 36
, for example, 1.5 V is applied to the word line WL and −1 V is applied to the bit line BL. Thereby, the PN junction of the drain
20
is forward biased, and holes are emitted to the bit line BL.
When data is read, as shown in
FIG. 37
, for example, 1.5 V is applied to the word line WL, 0.2 V is applied to the bit line BL, and the transistor composing the memory cell MC is turned on. Thresholds of the transistor when holes are accumulated in the channel body
28
and when holes are not accumulated therein are different because of a back bias effect. Accordingly,as shown in
FIG. 38
, the current characteristic of the transistor varies according to data. By detecting this difference in current, data can be read. Since the voltage of the bit line BL is low when data is read, the transistor of the memory cell MC operates in a linear region. Hence, impact ionization does not occur. Consequently, holes are not generated, and data in the memory cell MC is not destroyed. Namely, in the FBC structured memory cell MC, non-destructive read-out of data is possible.
Note that, in the non-selected memory cell MC in the memory cell array, −1.5 V is applied to the word line WL and 0 V is applied to the bit line BL.
Next, the entire configuration of a semiconductor memory device is explained which uses the memory cell array of the FBC memory.
FIG. 39
is a layout showing the configuration of such a semiconductor memory device. The FBC memory aims at replacing the DRAM, and therefore, similarly to the DRAM, it performs address signal multiplexing by a /RAS signal and a /CAS signal. An art regarding this address signal multiplexing is disclosed, for example, in document 2 (Kiyoo Itoh, “VLSI Memory”, Baifukan, p97, 1995).
As shown in
FIG. 39
, a memory cell array
100
includes the memory cells MC with the aforementioned configuration, a row decoder
102
is provided on one end side in a word line WL direction thereof, and a bit line selector
104
is provided on one end side in a bit line BL direction thereof.
An address signal inputted from an ADDRESS terminal is inputted to a row address buffer
110
and a column address buffer
112
. The row address buffer
110
sends out the inputted address signal (which is a row address signal) to a predecoder
120
based on the /RAS signal, and the row address signal is inputted to the row decoder
102
via the predecoder
120
. The row decoder
102
selects the word line WL based on the row address signal.
Meanwhile, the column address buffer
112
sends out the inputted address signal (which is a column address signal) to the bit line selector
104
based on the /CAS signal. The bit line selector
104
selects the bit line BL based on the column address signal, and connects the selected bit line BL to a sense unit
130
.
Program data is inputted from a DIN pad to this semiconductor memory device and sent out to the sense unit
130
via a data input buffer
140
. On the other hand, read data sensed in the sense unit
130
is outputted to the outside of this semiconductor memory device from a DOUT pad via a data output buffer
150
and an off-chip driver
152
. Inside the semiconductor memory device,in addition to these, a controller
160
for generating various control signals and a voltage generating circuit
162
for generating various internal voltages are provided.
A plurality of sense units
130
are connected to the bit line selector
104
.
FIG. 40
is a diagram showing a circuit configuration of one sense unit
130
and circuit configurations of its related circuits. As shown in
FIG. 40
, the one sense unit
130
includes a sense amplifier
200
, a latch circuit
202
, and an MIS transistor Tr
200
.
The sense amplifier
200
detects a cell

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