Semiconductor memory device, and method of checking the...

Details Semiconductor memory device, and method of checking the... Semiconductor memory device, and method of checking the...

1999-03-18

2002-04-16

Ton, David (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

C714S763000, C714S764000

Reexamination Certificate

active

06374381

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, and a method of checking the semiconductor device and a method of using the same, and more specifically to a semiconductor memory device having an error detection/ correction function, and a method of checking the semiconductor memory device and a method of using the same.
2. Description of the Related Art
Conventionally, a semiconductor device often includes an error checking and correcting circuit (hereinafter referred to ECC.) other than a semiconductor memory for storing data. Japanese Patent Laid-Open Publication No. Hei01-209552 discloses such a semiconductor memory device. In accordance with the semiconductor device, even if any error happens in data upon write and read operation of the data, the semiconductor memory device checks the data and corrects the error in itself to improve reliability thereof.
FIG. 10
illustrates an example of such a semiconductor device as the type described above. The semiconductor memory device includes an address register
101
, a write data register
102
, an error correction code generation circuit
103
, a memory circuit
104
, a changeover circuit
105
, an error detection circuit
106
, an error detection flag register
107
, an error correction circuit
108
, a read data register
109
, and a test mode register
110
.
The semiconductor memory device includes an external device (not shown) connected thereto through a bus (not shown) connected with the address register
101
, the write data register
102
, the error detection flag register
107
, the read data register
109
, and the test mode register
110
.
When the external device connected with the semiconductor memory device writes data in the memory circuit
104
, a signal indicative of an ordinary mode is applied to a test mode register
110
. The test mode register
110
after receiving the signal applies it to the switching circuit
105
as a control signal. The switching circuit
105
after receiving the control signal h
2
indicative of the foregoing signal, it connects the memory circuit
104
to the error detection circuit
106
and the error correction circuit
108
.
Thereafter, the external device applies the data to be written in the memory circuit
4
to the write data register
102
. The write data register
102
after receiving the data applies the data to the error correction code generating circuit
103
. The error correction code generation circuit
103
generates an error correction code for the foregoing data. Thereafter, the error correction code generation circuit
103
applies the generated error correction code to the foregoing data, and sends it to the memory circuit
104
as write data h
3
.
Upon writing data the external device applies a signal indicative of an instruction of read operation and of address. The address register
101
after receiving the foregoing signal applies it to the memory circuit
104
as an address signal h
1
. The memory circuit
104
after receiving the address signal hi stores write data h
3
in an memory area corresponding to an address indicated by the address signal h
1
. Upon reading the data the external device applies the signal indicative of an instruction of read operation and of an address to the address register
101
. The address register
101
after receiving the foregoing signal applies it to the memory circuit
104
as the address signal h
1
. The memory circuit
104
after receiving the address signal h
1
reads the data from a memory area corresponding to the address indicated by the address signal h
1
, and sends the data to the switching circuit
105
as read data h
4
. The switching circuit
105
sends the read data h
4
received from the memory circuit
104
to the error detection circuit
106
and the error correction circuit
108
.
The error detection circuit
106
judges based upon an error correction code added to the read data h
4
whether or not any error is existent in the red data h
4
. If the read data h
4
has any error, then the error detection circuit
106
sends a flag indicative of error detection to the error detection flag resistor
107
. The error detection flag register
107
holds the foregoing flag and informs the outside of happening of any error.
Simultaneously, the error detection circuit
106
sends a detection result indicative of the detection of any error to the error correction circuit
108
. The error correction circuit
108
corrects the error in the read data h
4
based upon the detection result. Thereafter, the error correction circuit
108
sends the read data h
4
subject to the error correction to the read data register
109
.
FIG. 11
illustrates such an error detection circuit
106
and an error correction circuit
108
. The illustrated error detection circuit
106
and error correction circuit
108
checks presence of any error, the number of error bits, position of any error bit based upon a parity check matrix H represented by a formula 1. The error detection circuit
106
includes a syndrome generation circuit
106
-
1
and a syndrome decode circuit
106
-
2
as illustrated in FIG.
11
.
H
=
❘
 
⁢
0
1
1
1
1
0
0
1
0
1
1
0
1
0
1
1
0
1
0
0
1
⁢
 
❘
(
1
)
The syndrome generation circuit
106
-
1
is to generate a syndrome value using the read data h
4
, an example of which is illustrated in FIG.
12
. The syndrome generation circuit
106
-
1
includes EXOR (exclusive or)
106
A to
106
J. When the read data h
4
comprises bits x
0
to x
6
, the syndrome generation circuit
106
-
1
calculates syndrome values s
0
, s
1
and s
2
using the following formula. In the read data h
4
, x
0
to x
3
are information bits corresponding to the data, and x
4
to x
6
inspection bits corresponding to the error correction code.
s
0
=x
1
*x
2
*x
3
*x
4
s
1
=x
0
*x
2
*x
3
*x
5
s
2
=x
0
*x
1
*x
3
*x
6
Herein, a code “*” in the foregoing formulae represents logical sum. Thereafter, the syndrome generation circuit
106
-
1
outputs the calculated syndrome values s
0
, s
1
and s
2
from EXOR gates
106
C,
106
F and
106
J to the syndrome decode circuit
106
-
2
.
The syndrome decode circuit
106
-
2
decodes the syndrome values s
0
, s
1
and s
2
and calculates the presence of any error, the number of error bits and the position of the error bit, and so on. The syndrome decode circuit
106
-
2
includes inverters
106
K to
106
M, a NOR gate
106
N, an inverter
106
P and NAND gates
106
Q to
106
T.
The syndrome decode circuit
106
-
2
after receiving the syndrome values s
0
, s
1
and s
2
outputs an error detection signal EF as the foregoing flag from the inverter
106
P using the following formulae and simultaneously generates bits y
0
to y
6
using the following formula together with the error correction circuit
108
including the EXOR gates
108
A to
108
D.
y
0
=x
0
*((−s
0
)·s
1
·s
2
)
y
1
=x
1
*(s)·(−s
1
)·s
2
)
y
2
=x
2
*(s
0
·s
1
·(−s
2
)
y
3
=x
3
*(s
0
·s
1
·s
2
)
y
4
=x
4
*(s
0
·(−s
1
)·(−s
2
))
y
5
=x
5
*((−s
0
)·s
1
·(−s
2
))
y
6
=x
5
*((−s
0
)·(−s
1
)·(−s
2
))
EF=s
0
+s
1
+s
2
In the foregoing eight formulae, a code “−” represents logical inversion and a code “+” represents logical sum. In
FIG. 12
an error correction circuit for bits y
4
to y
6
corresponding to check bits x
4
to x
6
is omitted.
The error detection circuit
106
sends the foregoing flag generated as such to the error detection flag register
107
. If there is no error, then the foregoing flag indicates “0” while if there is any error, then the foregoing flag indicates “1”. The error correction circuit
108
sends the generated bits y
0
to y
3
to the read data register
109
as the read data h
4
. Such an error correction code generation circuit
103
, error detection circuit
106
and error correction circuit
108
constitute the ECC circuit.
For checking whether or not the

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