Semiconductor memory device and method of burn-in testing

Details Semiconductor memory device and method of burn-in testing Semiconductor memory device and method of burn-in testing

1999-05-19

2000-09-05

Dinh, Son T.

Static information storage and retrieval

Read/write circuit

Testing

36518905, 365194, G11C 700

Patent

active

061153044

ABSTRACT:
A write circuit outputs a write con and to a memory cell in response to a data input signal. A decoder decodes an address input signal and outputs an address command to the memory cell. A counter outputs a signal to the decoder, the signal delaying decode timing in response to a control signal inputted at the time of a burn-in test. Therefore, the counter cancel a late write cycle by delaying an operation cycle of the decode timing against an operation cycle of a write command signal from the write circuit that is transmitted to the memory cell.

REFERENCES:
patent: 5471429 (1995-11-01), Lee et al.
patent: 5638331 (1997-06-01), Cha et al.
patent: 5680362 (1997-10-01), Parris et al.
patent: 5802001 (1998-09-01), Kim
patent: 5949724 (1999-09-01), Kang et al.

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