Semiconductor memory device and method for testing memory...

Details Semiconductor memory device and method for testing memory... Semiconductor memory device and method for testing memory...

2006-02-07

2008-08-26

Kerveros, James C (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

Reexamination Certificate

active

07418638

ABSTRACT:
There is provided a memory device in which memory cells may be tested using several different test data patterns. The memory device may include a switch unit, a plurality of storage units, and a selector. The switch unit may transfer bits of data received in response to a mode control signal to memory cells or transfers bits of test data to the memory cells. The plurality of storage units respectively stores bits of test data in response to bits of an input control signal. The selector applies test data stored in one of the storage units to the switch unit in response to the input control signal.

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patent: 2004/0153910 (2004-08-01), Thalmann et al.
patent: 05-012900 (1993-01-01), None
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