Semiconductor memory device and method for reading...

Details Semiconductor memory device and method for reading... Semiconductor memory device and method for reading...

2008-05-20

2008-05-20

Phung, Anh (Department: 2824)

Static information storage and retrieval

Read/write circuit

Precharge

C365S200000, C365S218000

Reexamination Certificate

active

10561965

ABSTRACT:
A semiconductor memory device having a dummy memory cell and a reading method of the same, wherein provision is made of a memory cell11connected to a word line WL and a pair of bit lines BL and xBL, a dummy memory cell12connected to a word line WL and a pair of dummy bit lines DBL and xDBL, and a word line driver13for activating the word line at a common timing, and when the data is read out from the memory cell, a timing of the reading of the data is determined in accordance with a level of the dummy bit lines connected to the dummy memory, and when a voltage difference of a pair of dummy bit lines becomes a threshold voltage, the word line driver deactivates the word line and precharges the dummy bit lines.

REFERENCES:
patent: 5903575 (1999-05-01), Kikuda
patent: 6314044 (2001-11-01), Sasaki et al.
patent: 2007/0047349 (2007-03-01), Tokito
patent: 06-349280 (1994-12-01), None
patent: 09-128958 (1997-05-01), None
patent: 2001-521262 (2001-11-01), None
patent: 2001-351385 (2001-12-01), None
International Search Report mailed Nov. 16, 2004.

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