Static information storage and retrieval – Read/write circuit – Differential sensing
Reexamination Certificate
2001-10-03
2003-02-25
Dinh, Son T. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Differential sensing
C365S206000, C365S207000, C365S230060
Reexamination Certificate
active
06525979
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory device and a method for reading information from the semiconductor memory device.
Recent dynamic random access memory devices (DRAMs) have higher integration, larger capacity, and less power consumption. Due to the higher integration of memory cell arrays, the memory cells included in the memory cell arrays have become smaller. This leads to a tendency in which the amount of charge accumulates as cell information in cell capacitance of each memory cell decreases.
In such DRAM, power consumption is reduced by prolonging a self-refresh operation or by prolonging an external refresh operation. The DRAM has a dummy word line and a coupling capacitor to read normal cell information based on a small voltage output from a memory cell. The coupling capacitor is located between the dummy word line and a bit line. To read cell information, the dummy word line is selected to increase the voltage of the bit line in accordance with the charge of the capacitor and add the increased voltage to the small voltage read to the bit line. In such DRAM, improved refresh characteristics and higher integration are required.
FIG. 1
is a schematic circuit diagram of a conventional semiconductor memory device (DRAM) provided with a function for complementing cell information with a dummy line.
A cell array
1
includes a plurality (two in
FIG. 1
) of memory cells
2
a
,
2
b
. The memory cell
2
a
is connected to an intersection between a bit line BL and a word line WL
0
. The memory cell
2
b
is connected to an intersection between an inverting bit line /BL and a word line WL
1
.
The memory cell
2
a
includes a cell transistor Tr and a cell capacitance C
1
. The cell transistor Tr includes a first terminal connected to the bit line BL, a second terminal connected to the cell capacitance C
1
, and a gate connected to the word line WL
0
. The cell capacitance C
1
has a first electrode connected to the cell transistor Tr and a second electrode supplied with a predetermined cell plate voltage. The cell plate voltage is, for example, one half the voltage of a cell power supply ViiC/2, which is supplied to the cell array
1
(hereafter referred to as ViiC/2 and depicted in
FIG. 1
as ½ ViiC)
A sense amplifier
3
is connected to the bit lines BL, /BL to amplify the cell information read to the bit lines BL, /BL. The sense amplifier
3
receives activation voltages SAP, SAN, which are generated by a sense amplifier voltage generation circuit
4
. The sense amplifier voltage generation circuit
4
receives a latch enable signal (sense amplifier activation signal) LE and generates the activation signals SAP, SAN based on the latch enable signal LE. The sense amplifier
3
is activated and inactivated based on the latch enable signal LE.
A dummy cell
5
a
is connected to an intersection between a bit line BL and a dummy word line DWL
0
. A dummy cell
5
b
is connected to an intersection between the inverting bit line /BL and a dummy word line DWL
1
. The dummy cells
5
a
,
5
b
have the same configuration as the memory cell
2
a.
A row address decoder and a word driver (not shown) select one of the word lines WL
0
, WL
1
based on a row address signal. Further, the row address decoder and a dummy word driver (not shown) select one of the dummy word lines DWL
0
, DWL
1
.
For example, when the memory cell
2
a
connected to the bit line BL is selected, the dummy word line DWL
0
is selected to increase the voltage of the dummy word line DWL
0
from power supply voltage Vss to power supply voltage Vii. When the memory cell
2
b
connected to the inverting bit line /BL is selected, the dummy word line DWL
1
is selected to increase the voltage of the dummy word line DWL
1
from the lower power supply voltage Vss to the high power supply voltage Vii. The high power supply voltage Vii is supplied to peripheral circuits, such as the row address decoder, the word driver, and the dummy word driver, from outside the DRAM
100
. The high power supply voltage Vii is decreased to generate stable cell power supply voltage ViiC.
A read operation performed by the DRAM
100
will now be discussed with reference to
FIGS. 2A and 2B
.
FIG. 2A
is a waveform chart of the DRAM
100
taken when cell information “0” is read from the memory cell
2
a
.
FIG. 2B
is a waveform chart of the DRAM
100
taken when cell information “1” is read from the memory cell
2
a.
The reading of cell information “0” will first be discussed.
FIG. 2A
shows voltage changes of the bit lines BL, /BL, the word line WL
0
, the dummy word line DWL
1
, and the latch enable signal LE. In this case, the voltage Vst at a storage node between the cell transistor Tr and a capacitor C
1
of the memory cell
2
a
corresponds to the low power supply voltage Vss.
Prior to an operation for reading cell data, the bit lines BL, /BL are precharged to voltage ViiC/2 by a precharge circuit. The voltage of the dummy word line DWL
0
is reset to the lower power supply voltage Vss.
Then, the word line WL
0
is selected based on the row address signal and the voltage at the word line WL
0
is increased from the low power supply voltage Vss to a step up voltage Vpp. In this state, when the voltage at the word line WL
0
increases from the lower power supply voltage Vss by a threshold value Vthcell of the cell transistor Tr, cell information “0” is read to the bit line BL from the memory cell
2
a
and the voltage at the bit line BL decreases from ViiC/2.
In this state, when the dummy word line DWL
0
is selected and the voltage at the dummy word line DWL
0
is increased from the lower power supply voltage Vss to the high power supply voltage Vii, the charge of the dummy cell
5
a
increases the voltage at the bit line BL. The cell capacitor of the dummy cell
5
a
is set so that the increased voltage at the bit line BL is recognized as a low level by the sense amplifier
3
. The cell capacitance of the dummy cell
5
b
is also set in the same manner. A differential voltage between the bit lines BL, /BL is amplified by the sense amplifier
3
that is activated by the latch enable signal LE. As a result, the voltage at the bit line BL changes to the lower power supply voltage Vss and cell information “0” is output from the bit line BL.
When cell information “1” is stored in the memory cell
2
a
, the voltage at the storage node between the cell transistor Tr and the capacitor C
1
of the memory cell
2
a
corresponds to the cell power supply voltage ViiC.
In the state of
FIG. 2B
, the bit lines BL, /BL are precharged to the voltage ViiC/2 by the precharge circuit prior to the operation for reading the cell information. The dummy word lines DWL
0
, DWL
1
are reset to the lower power supply voltage Vss.
Then, the word line WL
0
is selected based on the row address signal and the voltage at the word line WL
0
is increased from the low power supply voltage Vss to the step up voltage Vpp. In this state, when the voltage at the word line WL
0
increases from the precharge voltage ViiC/2 by the threshold value Vthcell of the cell transistor Tr, cell information “1” is read to the bit line BL from the memory cell
2
a
and the voltage at the bit line BL increases from the precharge level (ViiC/2).
In this state, when the dummy word line DWL
0
is selected and the voltage at the dummy word line DWL
0
is increased from the lower power supply voltage Vss to the high power supply voltage Vii, the charge of the dummy cell
5
a
increases the voltage at the bit line BL. This increases the differential voltage between the bit lines BL, /BL and effectively increases the charge of the cell. Thus, the interval for refreshing the memory cells
2
a
,
2
b
is lengthened.
The differential voltage between the bit lines BL, /BL is amplified by the sense amplifier
3
that is activated by the latch enable signal LE. As a result, the voltage at the bit line BL shifts to the high power supply voltage ViiC and cell information “1” is output from the bit line BL.
The threshold value voltage Vthcell
Armstrong Westerman & Hattori, LLP
Dinh Son T.
Fujitsu Limited
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